Mux Diagram For Rgmii0 And Vin1B; Soc Pinmux For Spi2 And Uart3; Mux Diagram For Spi2 And Uart3 - Texas Instruments DRA72 Series User Manual

Signal Multiplex Logic
Mux J: Selects between Gig Ethernet and expansion, as shown in
the IO expander #2 and bit P4, defaulting to Gig Ethernet.
SoC
4.7 SPI2 and UART3 Selection (Mux K)
Figure 19 is part of the SoC pinmux table for SPI2. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• SPI Serial Bus (SPI2): SCLK, D[1:0], CS[0]
• UART Serial Bus (UART3): TXD, RXD, CTSN, RTSN
Mux K: Selects between Bluetooth (COM8Q module) and expansion interface, as shown in
selection is made using the IO expander #2 and bits P16, defaulting to expansion.
SoC
30
DRA72x EVM CPU Board User's Guide
A1
RGMII0_TXC, _TXCTL, _TXD[3:0],
_RXC, RXCTL, _RXD[3:0]
UART3_RXD, _TXD
MDIO_MCLK, _D
Figure 18. Mux Diagram for RGMII0 and VIN1B
Figure 19. SoC Pinmux for SPI2 and UART3
A1=B1 or A1=B2
A1
SPI2_SCLK, _D[1:0], _CS[0]
Figure 20. Mux Diagram for SPI2 and UART3
Copyright © 2016, Texas Instruments Incorporated
Figure
RGMII0, MDIO
A1=B1 or A1=B2
RGMII0_TXC, _TXCTL, _TXD[3:0],
CBT16212
_RXD, _RXCTL, _RXD[3:0]
MDIO_MCLK, _D
B1
Mux
J
VIN1B
VIN1B_CLK, _VS, _HS, _DE, _DA[7:0]
B2
CBT3257 UART3
UART3_TX, _RX, _CTS, _RTS
B1
Mux
K SPI2
SPI2_SCLK, _D[1:0], _CS[0]
B2
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18. The selection is made using
Ethernet
Expansion
Connector
Figure
COM8Q
Connector
Expansion
Connector
SPRUIB9 – December 2016
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20. The