Nvidia MCP 78S User Manual page 56

EBDA...etc.
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Updates CMOS memory size from memory found in memory test. Allocates
memory for Extended BIOS Data Area from base memory. Programming
the memory hole or any kind of implementation that needs an adjustment
in system RAM size if needed.
60 Initializes NUM-LOCK status and programs the KBD typematic rate.
Initialize Int-13 and prepare for IPL detection.
75
Initializes IPL devices controlled by BIOS and option ROMs.
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7C Generate and write contents of ESCD in NVRam.
Log errors encountered during POST.
84
85 Display errors to the user and gets the user response for error.
87
Execute BIOS setup if needed / requested. Check boot password if
installed.
8C Late POST initialization of chipset registers.
8D Build ACPI tables (if ACPI is supported)
Program the peripheral parameters. Enable/Disable NMI as selected
8E
90
Initialization of system management interrupt by invoking all handlers.
Please note this checkpoint comes right after checkpoint 20h
Clean-up work needed before booting to OS
A1
A2
Takes care of runtime image preparation for different BIOS modules. Fill
the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ
Routing Table. Prepares the runtime language module. Disables the
system configuration display if needed.
A4 Initialize runtime language module. Display boot option popup menu.
A7
Displays the system configuration screen if enabled. Initialize the CPU's
before boot, which includes the programming of the MTRR's.
A9 Wait for user input at config display if needed.
AA Uninstall POST INT1Ch vector and INT09h vector
Prepare BBS for Int 19 boot. Init MP tables.
AB
AC
End of POST initialization of chipset registers. De-initializes the ADM
module.
B1
Save system context for ACPI. Prepare CPU for OS boot including final
MTRR values.
00 Passes control to OS Loader (typically INT19h).
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