Nvidia MCP 78S User Manual page 54

M/b for socket am2+ quad core amd processor

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POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during the BIOS preboot

process. The following table describes the type of checkpoints that may occur

during the POST portion of the BIOS:

Checkpoint

Start reading the recovery file cluster by cluster.

Disable L1 cache.

Check the validity of the recovery file configuration to the current

configuration of the flash part.

Make flash write enabled through chipset and OEM specific method. Detect

proper flash part. Verify that the found flash part size equals the recovery

file size.

The recovery file size does not equal the found flash part size.

Erase the flash part.

Program the flash part.

The flash has been updated successfully. Make flash write disabled.

Disable ATAPI hardware. Restore CPUID value back into register. Give

control to F000 ROM at F000:FFF0h.

Description

Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS,

POST, Runtime data area. Also initialize BIOS modules on POST entry and

GPNV area. Initialized CMOS as mentioned in the Kernel Variable

"wCMOSFlags."

Check CMOS diagnostic byte to determine if battery power is OK and CMOS

checksum is OK. Verify CMOS checksum manually by reading storage area.

If the CMOS checksum is bad, update CMOS with power-on default values

and clear passwords. Initialize status register A.

Initializes data variables that are based on CMOS setup questions.

Initializes both the 8259 compatible PICs in the system

Initializes the interrupt controlling hardware (generally PIC) and interrupt

vector table.

Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the

POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt.

Traps INT1Ch vector to "POSTINT1ChHandlerBlock."

Fixes CPU POST interface calling pointer.

Initializes the CPU. The BAT test is being done on KBC. Program the

keyboard controller command byte is being done after Auto detection of

KB/MS using AMI KB-5.

Early CPU Init Start -- Disable Cache – Init Local APIC

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