Nvidia MCP 78S User Manual page 52

M/b for socket am2+ quad core amd processor

Table of Contents

Post BIOS Beep Code

Number of Beeps

Debug Port Post Code

Bootblock Initialization Code Checkpoints

The Bootblock initialization code sets up the chipset, memory and other components

before system memory is available. The following table describes the type of

checkpoints that may occur during the bootblock initialization portion of the BIOS

Checkpoint

Before D0

APPENDIX II

Memory refresh timer error.

Parity error in base memory (first 64KB block)

Base memory read/write test error

Motherboard timer not operational

Processor error

8042 Gate A20 test error (cannot switch to protected mode)

General exception error (processor exception interrupt error)

Display memory error (system video adapter)

AMIBIOS ROM checksum error

CMOS shutdown register read/write error

Cache memory test failed

If boot block debugger is enabled, CPU cache-as-RAM functionality is

enabled at this point. Stack will be enabled from this point.

Early Boot Strap Processor (BSP) initialization like microcode update,

frequency and other CPU critical initialization. Early chipset initialization is

done.

Early super I/O initialization is done including RTC and keyboard controller.

Serial port is enabled at this point if needed for debugging. NMI is disabled.

Perform keyboard controller BAT test. Save power-on CPUID value in scratch

CMOS. Go to flat mode with 4GB limit and GA20 enabled.

Verify the boot block checksum. System will hang here if checksum is bad.

Disable CACHE before memory detection. Execute full memory sizing

module. If memory sizing module not executed, start memory refresh and

do memory sizing in Boot block code. Do additional chipset initialization.

Re-enable CACHE. Verify that flat mode is enabled.

Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.

given to it. BIOS now executes out of RAM. Copies compressed boot block

Description

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