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2
Description
The LMG3410EVM-031 operates as a daughter card as part of a larger custom designed system or with
the LMG34XX-BB-EVM breakout motherboard.
2.1
LMG3410EVM-031
The LMG3410EVM-031 configures two LMG3410R150 GaN FETs in a half bridge. All the bias and level
shifting components are included, allowing low side referenced signals to control both FETs. High
frequency bypass capacitors are included on the power stage in an optimized layout to minimize parasitic
inductance and reduce voltage overshoot.
There are 7 logic pins on the FET card.
PIN
AGND
12V
5V
FA_2
FA_1
Q2
Q1
There are 3 power pins on the FET card.
PIN
VSW
VDC
PGND
Q1
FA_1
Q2
FA_2
SNOU168 – June 2019
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Table 1. Logic Pin Function Description
DESCRIPTION
Logic and bias power ground return pin. Functionally isolated from PGND.
Auxiliary power input for Q2. Used as auxiliary power input for Q1 when the LMG3410EVM-031 is
configured in bootstrap mode.
Auxiliary power input for the LMG3410EVM-031. Used to power logic isolators. Used as input bias power
of LMG3410R050 devices when configured in isolated power mode.
FAULT signal from bottom LMG3410R150 Q2. Pin is either pulled to AGND or 5V.
FAULT signal from top LMG3410R150 Q1 Pin is either pulled to AGND or 5V.
AGND referenced logic gate signal input for bottom LMG3410R150 Q2. Compatible with both 3.3V and
5V logic.
AGND referenced logic gate signal input for top LMG3410R150 Q1. Compatible with both 3.3V and 5V
logic.
Table 2. Power Pin Function Description
12V
LMG3410
VDD
FAULT
12V
LMG3410
VDD
FAULT
Figure 1. Simplified LMG3410EVM-031 Schematic
Copyright © 2019, Texas Instruments Incorporated
DESCRIPTION
Switch node of the half bridge
Input DC voltage of the half bridge
Power ground of the half bridge. Connected to AGND.
PGND
LMG3410R150-031 EVM User Guide
Description
VDC
VSW
5
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