I 2 C Bus Switch - Xilinx AC701 User Manual

Table 1-21
Table 1-21: FPGA to LCD Header Connections
References
The datasheet for the Displaytech S162DBABC LCD can be found at
http://www.displaytech-us.com/products/charactermodules.php. Choose the S162D
model full spec download arrow.
2
I C Bus Switch
[Figure
The AC701 board implements a single I
IIC_SDA_SCL), which is routed through a Texas Instruments PCA9548 1-to-8 channel I
switch (U49). The I
I
target back-side device.
The AC701 board I
X-Ref Target - Figure 1-27
User applications that communicate with devices on one of the downstream I
must first set up a path to the desired bus through the U52 bus switch at I
0b01110100.
AC701 Evaluation Board
UG952 (v1.0) October 23, 2012
lists the connections between the FPGA and the LCD header.
FPGA Pin Schematic Net
(U1)
L25 LCD_DB4_LS
M24 LCD_DB5_LS
M25 LCD_DB6_LS
L22 LCD_DB7_LS
L24 LCD_RW_LS
L23 LCD_RS_LS
L20 LCD_E_LS
1-2, callout 19]
2
C switch can operate at speeds up to 400 kHz. The U49 bus switch at
2
C address 0x74/0b01110100 must be addressed and configured to select the desired
2
C bus topology is shown in
U1
FPGA
Bank 14
(3.3V)
IIC_SDA/SCL_MAIN
www.xilinx.com
LCD Header Pin
Name (J23)
4
3
2
1
10
11
9
2
C port on the FPGA (IIC_SDA_MAIN,
Figure
U52
PCA9548
1 2 C 1-to-8
Bus Switch
0x74
2
Figure 1-27: I C Bus Topology
Feature Descriptions
1-27.
CH0 - USER_CLK_SDL/SCL
CH1 - FMC_HPC_IIC_SDA/SCL
CH2 - (NOT USED)
CH3 - EEPROM_IIC_SDA/SCL
CH4 - SFP_IIC_SDA/SCL
CH5 - IIC_SDA/SCL_HDMI
CH6 - IIC_SDA/SCL_DDR3
CH7 - SI5324_SDA/SCL
UG952_C1_27_100312
2
C buses
2
C address 0x74/
2
C
45