1.2
Main PCB Block Diagram
HL-820/1020
Fig. 2-4 shows the block diagram of the main PCB.
A S I C
CPU Core
(MC68EC000)
Reset Circuit
Oscillator (15.3MHz)
BUS
INT
Address Decoder
DRAM Control
Program + Font ROM
512 Kbytes
Timer
RAM
(2.0 Mbytes)
FIFO
DATA EXTENSION
To PC
CDCC Parallel I/O
Soft Support
EEPROM (128
8 bits)
EEPROM I/O
Motor Driver
Engine Control I/O
To Panel Sensor PCB
Fig. 2-4
II-4