Memory; Fig 11 Fci Interface; Fig 12 Fci Connector Pin Order On Pwb - Nokia NPL-4 Series Manual

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EN
VBAT
VIO
GenIO_18
GenIO_22
UPP
GenIO_2
GenIO_25
Bottom View
Keypad-side FC conn.
Pad layout

Memory

For the MCU UPP includes ROM, 2 Kbytes, that is used mainly for boot code of MCU. To
speed up the
MCU operation small 64-byte cache is also integrated as a part of the MCU memory
interface. For program memory 8Mbit (512 x 16bit) PDRAM is integrated. RAM block can
Copyright © 2005 Nokia Corporation. All rights reserved.
Issue 2 05/05
Figure 11: FCI Interface
Terminal
FCI ASIP
Switch
+
ferrite
Short Circuit
protection
ferrite
ferrite
ferrite
Figure 12: FCI Connector Pin Order on PWB
1. Vout
2. GND
3. SDA
4. SCL
5.
1
System Module and User Interface
FC_Vout ferrite
Cout
FC_SDA ferrite
FC_SCL ferrite
FC_INT ferrite
FCIInt
NPL-4/5/
Functional Cover
Reg.
Cin
MCU
5
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