JVC GZ-MG40US Schematic Diagrams page 35

REAR(REAR IF) SCHEMATIC DIAGRAM
KEY_B
REG-CCD
SJIG_RST
REG_3.1V
DATA_OUT
CAM_3.1V
CHRG_EVR
REG_4.8V
ADP_L
REG_1.5V
T_BATT
GND
TO OP REG
D_BATT
REG_1.2V
DC_CHEK
DRV_3.3V
REG_CS
AL_3.1V
CLK_OUT
REG_2.5V
V_BATT
I_MTR
UNREG
REG+CCD
KEY_B
BATT_CHK
TO OP REG
BATT+
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
0 5 REAR(REAR IF)
R601
10k
S601 NSW0223-001X
HALF_SW
1 2
R602
3.3k
FULL_SW
R604
150k
4
3
R605
C604 5 6
39k
OPEN
TO MAIN IF(CN103)
CN6001
QGF0528F3-45X
1 KEY_B
2 REG-CCD
3 SJIG_RST
4 REG_3.1V
5 REG_3.1V
6 REG_3.1V
7 DATA_OUT
8 CAM_3.1V
9 CAM_3.1V
10 CHRG_EVR
11 REG_4.8V
12 REG_4.8V
13 REG_4.8V
14 ADP_L
15 REG_1.5V
16 REG_1.5V
17 REG_1.5V
18 T_BATT
19 GND
D601
20 GND
EMZ6.8N-X
3
21 GND
22 GND
1
2
23 GND
C602
OPEN
24 GND
25 GND
C603
0.1
26 GND
27 GND
28 D_BATT
29 REG_1.2V
30 REG_1.2V
31
REG_1.2V
32 DC_CHEK
33 DRV_3.3V
34
DRV_3.3V
35 DRV_3.3V
36
REG_CS
37
AL_3.1V
38 AL_3.1V
39
CLK_OUT
40 REG_2.5V
41 REG_2.5V
42
V_BATT
I_MTR
43
44
UNREGCHK
45
BL_POWER
[-] TP4
C601
[D] TP3
0.1
[T] TP2
R603
0
[+] TP1
BATTERY TERM
LY34726-001A
y40158001a_rev0.1
(No.YF109)2-34