JVC GZ-MG40US Schematic Diagrams page 26

MAIN(TG133) SCHEMATIC DIAGRAM
TO CCD(CN5001)
CN105
QGF0547C2-24X
REG_+15V 1
REG_+15V 2
REG_-7.5V 3
REG_-7.5V 4
CCD_CTL 5
GND
GND
GND
CCD_OUT
GND
GND
GND
RG 13
H1 14
H2 15
SUB 16
V1 17
V2 18
V3 19
V4 20
GND 21
G_RST 22
REG_3.1V 23
P_GYAMP 24
TO P.PRCS P_GYAMP
REG_3.1V
TO GYRO,
G_RST
P.PRCS
GND
TO DSP
CCD_CTL
TG_CS
CAM_CLK
TO OP DRV,
CDS,P.PRCS
CAM_OUT
TO SUB CPU
TG2_RST
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-25(No.YF109)
0 1 MAIN(TG133)
R5514
10
R5515
10
R5516
10
R5517
10
R5518
10
37 VDD3
38 SGMOD
39 VM
40 V2
41 V4
42 V1
43 VH
C5514
44 V3
1/35
C5511
45 SUB
T 0.1
D5501
46 VL
1SS355-X
47 DSGAT
R5511
48 VDD4
100k
L5507
NQR0129-002X
36 35 34 33 32 31 30 29
IC5501
CXD3602AR
TG/V-DRIVER
1 2 3 4 5 6 7 8
C5502 C5501
0.1
0.1