JVC GZ-MG40US Schematic Diagrams page 20

MAIN(DSP MEM) SCHEMATIC DIAGRAM
TO SUB CPU
FLSH_RST
TO MAIN IF
REG_3.1V
(CN103),
REG_2.5V
MPEG2,V I/O
GND
0
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-19(No.YF109)
L4302
OPEN
L4303
NQR0154-003X
C4304
4.7
C4303
T 100/4
1 MAIN(DSP MEM)
4
2
3
3
4
1
1
2
3
1
4
4
2
3
2
1
#:EXCHANGE PARTS LIST
IC4301
NonMEGA SG32M90TFIR4B11
MEGA SG32M90TFIR4B10
L4301
NQR0129-002X
C4301
4.7
RA4301
100k
SDR_DQ31
5
F880[2]
RA4301
100k
SDR_DQ30
7
CF PORT POWERUP
RA4301
100k
SDR_DQ29
6
CF PORT POWERUP
RA4302
100k
SDR_DQ28
6
USB PORT POWERUP
RA4302
100k
SDR_DQ27
5
CF PORT POWERUP
RA4302
100k
SDR_DQ26
8
CF PORT POWERUP
RA4301
100k
SDR_DQ25
8
CPU SELECT
RA4302
100k
SDR_DQ24
7
F89E[6]
RA4303
100k
SDR_DQ23
6
F89E[5:3]
RA4303
100k
SDR_DQ22
8
F89E[5:3]
RA4303
100k
SDR_DQ21
5
F89E[5:3]
RA4304
100k
SDR_DQ20
5
RESERVED
RA4303
SDR_DQ19
100k
MEMORY WIDTH FOR
7
01: 16bit
RA4304
100k
SDR_DQ18
6
MEMORY WIDTH FOR
RA4304
01: 16bit
100k
SDR_DQ17
7
RA4304 F880[1]
100k
SDR_DQ16
8
F880[0]