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6 I/O PORTS (PPORT)
6.2 I/O Cell Structure and Functions
Figure 6.2.1 shows the I/O cell Configuration.
Pull-up/down
Pull-up/down
Control signal
Input signal
Input control signal
Output signal
Output control signal
Analog signal
LCD/analog signal
Analog control signal
Over voltage tolerant fail-safe type I/O cell
Refer to "Pin Descriptions" in the "Overview" chapter for the cell type, either the over voltage tolerant fail-safe
type I/O cell or the standard I/O cell, included in each port.
6.2.1 Schmitt Input
The input functions are all configured with the Schmitt interface level. When a port is set to input disable status
(PxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is placed into floating status.
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell
The over voltage tolerant fail-safe type I/O cell allows interfacing without passing unnecessary current even if a
voltage exceeding V
is applied to the port. Also unnecessary current is not consumed when the port is externally
DD
biased without supplying V
mum operating power supply voltage to the port.
6.2.3 Pull-Up/Pull-Down
The GPIO port has a pull-up/pull-down function. Either pull-up or pull-down may be selected for each port indi-
vidually. This function may also be disabled for the port that does not require pulling up/down.
When the port level is switched from low to high through the pull-up resistor included in the I/O cell or from high
to low through the pull-down resistor, a delay will occur in the waveform rising/falling edge depending on the time
constant by the pull-up/pull-down resistance and the pin load capacitance. The rising/falling time is commonly de-
termined by the following equation:
t
= -R
× (C
+ C
PR
INU
IN
t
= -R
× (C
+ C
PF
IND
IN
Where
t
:
Rising time (port level = low → high) [second]
PR
t
:
Falling time (port level = high → low) [second]
PF
V
:
High level Schmitt input threshold voltage [V]
T+
V
:
Low level Schmitt input threshold voltage [V]
T-
R
/R
: Pull-up/pull-down resistance [W]
INU
IND
C
:
Pin capacitance [F]
IN
C
:
Parasitic capacitance on the board [F]
BOARD
6-2
V
DD
control
R
/
V
INU
SS
R
IND
V
DD
∗ No diode is
connected at
V
the V
side.
DD
DD
V
SS
control
Figure 6.2.1 I/O Cell Configuration
. However, be sure to avoid applying a voltage exceeding the recommended maxi-
DD
) × ln(1 - V
/V
)
BOARD
T+
DD
) × ln(1 - V
/V
)
BOARD
T-
DD
Seiko Epson Corporation
Pull-up/down
Control signal
Input signal
Input control signal
Pxy
Output signal
Output control signal
LCD/analog signal
Analog control signal
Standard I/O cell
(Eq. 6.1)
V
DD
Pull-up/down
control
R
/
V
INU
SS
R
IND
V
DD
V
DD
V
DD
Analog signal
V
SS
control
S1C17W22/W23 TECHNICAL MANUAL
Pxy
(Rev. 1.3)
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