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MUX/DMUX
Figure
LINFO
LINF1
LINF14
LINF15
RIRO
The
queues
IBBO
guaranteed
MUX
The
corresponding
not received
not received
is
effort
When
when
or
low-priority
Figure
Cisco HyperSwitch
A100
B-2
ATOMSW
Block
B-i
CTL
SW
ATOM
Asynchronous
Output-buffer
CTL
Control
DMUX
Demultiplexer
LINF
interface
Line
MUX
Multiplexer
buffer
comprises
total
FJFO
32
Line
for
queues
IBG15/IBB15
Line
15
through
multicast
IBGM/input
from two
cells
multiplexes
FIFO
The
queue
first
from
the destination
line
from
The
lines
all
B-l
Table
queues
provides
number
the
of
stored
cells
in
number
the
of
stored in
cells
them
without
cells
saving
MUXIDMUX
B-2 shows
the
User Guide
Diagram
mode
transfer
modular
switch
Co
01
and
34
best
of
effort
guaranteed
buffer
guaranteed
FIFO
and two
queues
multicast
buffer
best
effort
and
lines
stores
temporarily
FIFO
of each
is
cell
queue
IBGMIBBM
From
however
FIFO
cells
in
guaranteed
queues
which
the conditions
in
these four
each
or best
guaranteed
effort
below
an
idle
queue
goes
card
block
diagram
FIFO
first-out
first-in
buffer
best
effort
IBGO/input
for multicast
buffer
IBBM
the
cells
in
multiplexed
when
back
output
pressure
when BP
the
cell
is
first
output
served
before
those
are
FIFO
served
types
are
FIFO
exceeds
threshold
queue
the system
discards
threshold
cell
BP
is
best
in
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