Timer Registers - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

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9.5

Timer Registers

Table 9-8 lists the memory-mapped Timer registers. All register offset addresses not listed in
should be considered as reserved locations, and the register contents should not be modified.
Offset Acronym
0h GPTMCFG
4h GPTMTAMR
8h GPTMTBMR
Ch GPTMCTL
18h GPTMIMR
1Ch GPTMRIS
20h GPTMMIS
24h GPTMICR
28h GPTMTAILR
2Ch GPTMTBILR
30h GPTMTAMATCHR
34h GPTMTBMATCHR
38h GPTMTAPR
3Ch GPTMTBPR
40h GPTMTAPMR
44h GPTMTBPMR
48h GPTMTAR
4Ch GPTMTBR
50h GPTMTAV
54h GPTMTBV
6Ch GPTMDMAEV
SWRU543 – January 2019
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Table 9-8. Timer Registers
Register Name
GPTM Configuration
GPTM Timer A Mode
GPTM Timer B Mode
GPTM Control
GPTM Interrupt Mask
GPTM Raw Interrupt Status
GPTM Masked Interrupt Status
GPTM Interrupt Clear
GPTM Timer A Interval Load
GPTM Timer B Interval Load
GPTM Timer A Match
GPTM Timer B Match
GPTM Timer A Prescale
GPTM Timer B Prescale
GPTM Timer A Prescale Match
GPTM Timer B Prescale Match
GPTM Timer A
GPTM Timer B
GPTM Timer A Value
GPTM Timer B Value
GPTM DMA Event
Copyright © 2019, Texas Instruments Incorporated
Timer Registers
Table 9-8
Section
Section 9.5.1
Section 9.5.2
Section 9.5.3
Section 9.5.4
Section 9.5.5
Section 9.5.6
Section 9.5.7
Section 9.5.8
Section 9.5.9
Section 9.5.10
Section 9.5.11
Section 9.5.12
Section 9.5.13
Section 9.5.14
Section 9.5.15
Section 9.5.16
Section 9.5.17
Section 9.5.18
Section 9.5.19
Section 9.5.20
Section 9.5.21
317
General-Purpose Timers