Appendix A: Timer 1 (T1) Control Registers; Timer 1 - Dual Compare Mode - Texas Instruments TMS370 Series Application Book

Timer 1 (T1) Control Registers
T1 is controlled and accessed through registers in the peripheral file. These registers are shown in Table 7
and are described in the TMS370 Family User's Guide. The bits shown in the shaded boxes in Table 7 are
privilege mode bits; they can only be written to in the privilege mode. The T1 operational mode block
diagrams are shown in Figure 22 and Figure 23.
Figure 22. Timer 1 – Dual Compare Mode
Prescaler/
Clock
Source
41 LSB
16-Bit
Counter
40 MSB
Reset
T1C1
RST ENA
T1 SW
4C.4
RESET
4C.1
4A.0
T1CR
RST ENA
T1EDGE DET
T1
Edge 4C.0
IC/CR
Select
Pin
284
Appendix A
16-Bit LSB 45
Capture/
Compare
Register
MSB 44
T1C2 INT FLAG
Compare =
Flag
4B.6
16
T1C1 INT FLAG
Flag
Compare =
4B.5
16-Bit
LSB 43
Compare *
Register
MSB 42
T1 OVRFL INT
Flag
4A.3
T1EDGE INT
ENA
Flag
4B.7
T1 EDGE
POLARITY 4C.2
4B.1
Output
T1C2
Enable
INT ENA
4C.5
T
T1C2
4B.0
O
OUT ENA
G
4C.6
G
T1C1
T1C1
INT ENA
L
OUT ENA
4C.3
E
T1CR
OUT ENA
4A.4
T1 OVRFL
INT ENA
Level 1 INT
4B.2
4F.6
Level 2 INT
INT ENA
T1EDGE
T1PWM
PIN