Epson S5U1C60N08D Manual page 18

Cmos 4-bit single chip microcomputer
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3 FUNCTION OPTION GENERATOR FOG6008
6 Input port pull down resistor
*** OPTION
NO.6 ***
--- I/P PORT PULL DOWN RESISTOR ---
K00
PLEASE SELECT NO.(1) ? 1
(Selection for K01–K03 and K10)
PLEASE SELECT NO.(1) ? 1
K20
PLEASE SELECT NO.(1) ? 2
(Selection for K21–K23)
PLEASE SELECT NO.(1) ? 2
K00
1. WITH RESISTOR
K01
1. WITH RESISTOR
K02
1. WITH RESISTOR
K03
1. WITH RESISTOR
K10
1. WITH RESISTOR
K20
2. GATE DIRECT
K21
2. GATE DIRECT
K22
2. GATE DIRECT
K23
2. GATE DIRECT
7 Output port output specification (R00–R03)
*** OPTION
NO.7 ***
--- O/P OUTPUT SPEC. (R00-R03) ---
R00
PLEASE SELECT NO.(1) ? 1
R01
PLEASE SELECT NO.(1) ? 1
R02
PLEASE SELECT NO.(1) ? 2
R03
PLEASE SELECT NO.(1) ? 2
R00
1. COMPLEMENTARY
R01
1. COMPLEMENTARY
R02
2. P-CH OPEN DRAIN
R03
2. P-CH OPEN DRAIN
12
1. WITH RESISTOR
2. GATE DIRECT
:
:
1. WITH RESISTOR
2. GATE DIRECT
:
:
SELECTED
SELECTED
SELECTED
SELECTED
SELECTED
SELECTED
SELECTED
SELECTED
SELECTED
1. COMPLEMENTARY
2. P-CH OPEN DRAIN
1. COMPLEMENTARY
2. P-CH OPEN DRAIN
1. COMPLEMENTARY
2. P-CH OPEN DRAIN
1. COMPLEMENTARY
2. P-CH OPEN DRAIN
SELECTED
SELECTED
SELECTED
SELECTED
Select whether input ports (K00–K03, K10 and
K20–K23) will each be supplemented with pull
down resistors or not. When "GATE DIRECT" is
selected, see to it that entry floating state does not
occur. Select "WITH RESISTOR" pull down
resistor for unused ports.
Moreover, the input port status is changed from
high level (V
DD
resistors, a delay of approximately 1 msec in
waveform rise time will occur depending on the
pull down resistor and entry load time constant.
Because of this, when input reading is to be
conducted, ensure the appropriate wait time with
the program.
The configuration of the pull down resistor circuit
is shown in Figure 3.3.2.
K
Fig. 3.3.2 Configuration of pull down resistor
Select the output specification for the output ports
(R00–R03).
Either complementary output or Pch open drain
output may be selected.
When output port is to be used on key matrix
configuration, select Pch open drain output.
For unused output ports, select complementary
output.
The output circuit configuration is shown in Figure
3.3.3.
Output
register
Complementary
Pch open drain
Fig. 3.3.3 Configuration of output circuit
EPSON
(DEVELOPMENT SOFTWARE TOOL FOR S1C60N08)
) to low (V
) with pull down
SS
V
DD
Data bus
Read signal
V
SS
S5U1C60N08D MANUAL
V
DD
R
V
SS

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