Panasonic KV-S1057C Service Manual page 72

On this system, the CPU (IC4) controls the operation of CIS (Contact Image Sensor), Motor (Conveyor Motor,PLATEN Motor), Sen-
sors' block (Paper, Starting, Door,Auto,Double Feed Detect) and Panel Block (LCD,LEDs, Switch) to execute scanning documents.
(Paper Feeding)
The CPU (IC4) provides the Motor Driver (IC19) with some motor-pulse signals to drive the Conveyor Motor to execute scan-
ning documents.
(Image Processing)
KV-S1027C/KV-SL1056/SL1055/SL1036/SL1035
1. This scanner has 2 CISs (CIS(F) and CIS (B)) so that both sides of document can be scanned independently.
At first, both CIS (F) and CIS (B) are driven by the drive pulses (CIS Transfer Gate pulse and CIS Transfer Gate Clock) that
are output from the pulse generation circuit in the CPU (IC4).
2. As the result of this, image analog signals "SIG" are output from the CIS (F) and the CIS (B) respectively.
3. The analog signals are alternately converted to digital signals (Digital Signal for Front, Digital Signal for Back by the AFE
(IC2,IC3) that operates as an A/D converter.
4. The converted digital signals are divided into two parts (Digital Signals for Front and Digital Signals for Back), and are stored
to the DDR2 Memory (IC20,IC21) temporarily by the CPU (IC4).
5. According to the command from the PC, DSP in the CPU (IC4) performs image processing such as shading, color conversion
(Only applied to color image data), and JPEG compression by using DDR2 Memory (IC20,IC21) that enables the intermediate
data (Only applied to color image data)
6. After handling the above process, the CPU (IC4) stores the data into the DDR2 Memory (IC20,IC21).
7. Controlled by USB Controller in the CPU (IC4), the processed data is transmitted from DDR2 Memory (IC20,IC21) to the PC
via the USB interface.
KV-S1057C/KV-SL1066
1. This scanner has 2 CISs (CIS(F) and CIS (B)) so that both sides of document can be scanned independently.
At first, both CIS (F) and CIS (B) are driven by the drive pulses (CIS Transfer Gate pulse and CIS Transfer Gate Clock) that
are output from the pulse generation circuit in the FPGA (IC43).
2. As the result of this, image analog signals "SIG" are output from the CIS (F) and the CIS (B) respectively.
3. The analog signals are alternately converted to digital signals (Digital Signal for Front, Digital Signal for Back by the AFE
(IC2,IC3) that operates as an A/D converter.
4. The digital signal output from AFE(IC2,IC3) is converted to a differential signal in FPGA(IC43).
The differential signals ( CIS(F) data and CIS(B) data) are output from FPGA(IC43) to CPU(IC4)
5. The converted digital signals are divided into two parts (Differential Signals for Front and Differential Signals for Back), and
are stored to the DDR2 Memory (IC20,IC21) temporarily by the CPU (IC4).
6. According to the command from the PC, DSP in the CPU (IC4) performs image processing such as shading, color conversion
(Only applied to color image data). In addition, JPEG compression is performed in PM-36(IC30).
7. After handling the above process, the CPU (IC4) stores the data into the DDR2 Memory (IC20,IC21).
8. Controlled by USB Controller (IC26), the processed data is transmitted from DDR2 Memory (IC20,IC21) to the PC via the
USB interface.
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