MSI EFINITY Series Manual page 46

M S-7395 M ainboard
M emory Information
This screen displays the current system memory capacity.
DRAM Remapping Above 4G
Ensure your operating system is 64bit, when set to [Enabled], the feature allows
your system identify more the 4GB memory. When set to [Disabled], you can use
only a maximum of 4GB.
Flex M emory mode
Flex memory mode provides the most flexible performance characteristics. The
bottommost DRAM memory (the memory that is lowest within the system memory
map) is mapped to dual channel operation; the topmost DRAM memory (the
memory that is nearest to the 8 GB address space limit), if any, is mapped to
single channel operation. Flex mode results in multiple zones of dual and single
channel operation across the whole of DRAM memory. To enable flex memory
mode, it is necessary to populate both channels.
Configuration DRAM Timing by SPD
Setting to [Enabled] enables DRAM CAS# Latency automatically to be determined
by BIOS based on the configurations on the SPD (Serial Presence Detect) EEPROM
on the DRAM module.
TCL
W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable.This controls the CAS latency, which determines the timing delay (in
clock cycles) before SDRAM starts a read command after receiving it. Smaller
clocks increase system performance while bigger clocks provide more stable
system performance.
TRAS
W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. This setting determines the time RAS takes to read from and write to
a memory cell.
TRCD
W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. W hen DRAM is refreshed, both rows and columns are addressed
separately. This setup item allows you to determine the timing of the transition
from RAS (row address strobe) to CAS (column address strobe). The less the
clock cycles, the faster the DRAM performance.
TRP
W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is
adjustable. This setting controls the number of cycles for Row Address Strobe
(RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to
accumulate its charge before DRAM refresh, refresh may be incomplete and
DRAM may fail to retain data. This item applies only when synchronous DRAM is
installed in the system.
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