Clock Architecture - Symmetricom XLi IEEE 1588 User Manual

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Clock Architecture

Figures 1 and 2 on the following pages provide a simplified view of the standard XLi's clock architecture.
Aux Ref
1,5,10 MHz
10 MHz Osc.
1 PPS A
1PPS B
Time and Clock
Code Input
Code Input
Figure 1: Functional Timing Block Diagram
XLi IEEE 1588 Clock
997-01510-03, Rev. C, 12/12/2006
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Aux Ref
DAC
1 PPS
Timing
Select
Recovery
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16.384 MHz Osc. PLL
Phase Measurement
Clock DPLL
200 MHz PLL
Phase Compare
Clock Machine
Code Generation
Rate Gen
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2
1
5
1 PPS
Output
Code Out
Rate Out
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1 PPS Out
Code Out
Rate Out
7