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Hardware Setup
CMOS Clearing (JP5)
After you have turned off your computer, clear the CMOS memory
by momentarily shorting pins 2-3 on jumper JP5, for a few seconds.
Then restore JP5 to the initial 1-2 jumper setting in order to recover
and retain the default settings.
CMOS Clearing
JP5 Setting
Note: You must unplug the ATX power cable from the ATX power
connector when performing the CMOS Clear operation.
Step 17. MULTI I/O ADDRESSES
Default settings for multi-I/O addresses are as follows:
Port
LPT1
COM1
COM2
Warning: If a default I/O address conflicts with other I/O
cards such as sound card, you must change one of the I/O
addresses to remedy to this address conflict. (I/O addresses
can be adjusted from the BIOS Setup Utility)
Step 18. CACHE CONFIGURATION
This Motherboard has a built-in 512KB/1MB Level 2 Pipelined Burst
cache onboard to improve the system performance.
The cache size and RAM locations are specified as follows:
Cache Size
1 MB
512 KB
Clear CMOS Data
Short pin 2-3 for
a few seconds
to clear the
CMOS
I/O Address
378H
3F8H
2F8H
Cache RAM
64K x 64
on U23,U16
64K x 64
on U23
34
SY-5EHM/5EH5 V1.3
Retain CMOS Data
Short pin 1-2
to retain new
1
2
3
settings
IRQ
7
ECP + EPP
4
3
TAG RAM
32K x 8
on U18
32K x 8
on U18
1
2
3
Status
Cacheable
Range
WT: 256 MB
WB: 128MB
WT: 128 MB
WB: 64 MB
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