Silicon Switch Processor (Ssp); Interface Processors - Cisco 7000 Series Hardware Installation And Maintenance Manual

Silicon Switch Processor (SSP)

The SSP is the optional high-performance silicon switch for Cisco 7000 series routers. The SSP
provides distributed processing and control for the interface processors, and communicates with and
controls the interface processors on the high-speed CxBus. The SSP determines the destination of a
packet and switches the packet, based on that decision.
The SSP is always installed in the backplane SP slot adjacent to the RP. A few seconds after bootup,
the enabled LED comes on to indicate that the SSP is enabled for operation.
One SSP (or SP) is required in each Cisco 7000 series router.
There are two hardware versions of the SSP: one with 512 KB of packet memory and another with
2 MB of packet memory (for installations requiring increased memory capacity).
Following are minimum system requirements for the SSP types:
•
The SSP with 512 KB of packet memory requires Cisco Internetwork Operating System
(Cisco IOS) Release 10.0, or later.
•
The SSP with 2 MB of packet memory requires Cisco IOS Release 10.0 or later. Cisco IOS
Releases 10.2(x) and 10.3(x) will provide the best use of the 2-MB SSP. (Detailed procedures for
upgrading your Cisco 7000 series router software are provided separately with the software
upgrade.)

Interface Processors

An interface processor comprises a modular, self-contained interface board and one or more network
interface connectors in a single 11 x 14-inch unit. All CxBus interface processors support Online
Insertion and Removal (OIR), so you can install and remove them without opening the chassis and
without turning off the chassis power. (The early serial interface processor, known as the SX-SIP or
PRE-FSIP, will not operate in the Cisco 7010; see the following Caution.) The RP, SP, and SSP,
which are required system components, always reside in the RP, SP, and SSP slots. (See Figure 1-3.)
The remaining three slots are available for any combination of the following interface processors:
•
AIP—ATM Interface Processor. For interface types and specifications, refer to the section "ATM
Connection Equipment" in the chapter "Preparing for Installation."
•
CIP—Channel Interface Processor. Any combination of one or two bus and tag and/or one or two
Enterprise System Connection (ESCON) interfaces. For bus and tag and ESCON interface
configurations and specifications, refer to the section "Channel Attachment Connection
Equipment" in the chapter "Preparing for Installation."
•
EIP—Ethernet Interface Processor with two, four, or six AUI ports, each of which operates at up
to 10 Mbps.
•
FEIP—For up to two 100BaseT, RJ-45 or Media Independent Interface (MII) ports. The
interfaces on an FEIP can both be configured at 100 Mbps, half duplex (HDX) or full duplex
(FDX), for a maximum aggregate bandwidth of 200 Mbps.
•
TRIP—High-speed (4 or 16 Mbps) Token Ring Interface Processor with two or four DB-9 ports.
•
FIP—High-speed (100 Mbps) FDDI Interface Processor with one single-attach or dual-attach
port (PHY A/PHY B) in any combination of single-mode and multimode ports (such as
single-single, multi-single, and so forth).
•
FSIP—Fast (up to 8 Mbps, or 16 Mbps aggregate with 8 ports) serial Interface Processor that
provides four or eight synchronous serial ports.
•
HIP—High-speed (up to 52 Mbps) Serial Interface Processor with a single HSSI port.
Physical Description
Product Overview 1-21