IBM System/370 145 Manual page 82

After the effective virtual storage address has been computed and
prior to performing translation using the tables, the TLB is
interrogated to determine whether or not i t contains the translated
address. The eight registers are inspected simultaneously. The segment
and page bits from the virtual storage address to be translated are
compared to the eight segment and page fields in the TLB registers. If
a match occurs, the real storage address is taken from the TLB register
and translation processing is finished. No additional CPU time is
required for the translation process when the real address is obtained
from the TLB. If the TLB does not contain the required translation, the
complete translation procedure, as previously described, is performed,
which requires four microseconds. .
During initial program reset, the virtual storage address and the
parity bit in each of the eight registers in the TLB are set to zero.
ThUS, no match can occur until new values are loaded as a result of the
translation process. The PURGE TLB instruction provides the capability
of clearing all eight TLB registers during system operation. In
general, this instruction must
be
issued when an entry in a page table
is invalidated, since the real storage address bits being invalidated
could
be
contained in the TLB. (The control program will purge the TLB
as required.) The TLB is also cleared when the DAT mode bit is turned
off, when control register 1 is changed, when segment or page size is
changed, and when certain mode changes are made by the DOS emulator
program.
since the TLB can hold eight translation addresses at any time, a
task can work with a given 16K or 32K of program and data during an
interval when i t has CPU control without invoking the table lookup
translation procedure after the eight required virtual storage addresses
have been translated.
Addresses Translated
All storage addresses that are explicitly designated by a program and
that are used by the CPU to refer to instructions or data in processor
storage are virtual storage addresses and are subject to address
translation. Thus, when DAT is operative, the starting and ending
storage addresses used with the program event recording feature are
virtual, as are the storage addresses stored in PSW's during
interruptions. Address translation is not applied to addresses that
explicitly designate protect key storage locations or to quantities that
are formed as storage addresses from the values designated in the base
and displacement fields of an instruction but that are not used to
address processor storage (shift instructions, for example). In
addition, address translation is not applied to the storage addresses in
CCW lists used for I/O operations.
Some of the storage addresses supplied to a program by the CPU are
virtual and some are real. Table 15.10.2 lists, for the Model 145,
those storage addresses designated by a program, either explicitly or
implicitly, that are virtual (and, therefore, are subject to
translation) and those storage addresses that are real or not used to
reference processor storage and, thus, are not translated. The table
also indicates which storage addresses supplied to a program are virtual
and thus, which are real.
72 A Guide to the IBM System/310 Model 145