IBM System/370 145 Manual page 206

4. The check-stop-control bit is on.
5~ CPO extended logout is specified and control register 15 points
to location 512 as the beginning of the CPU extended logout area.
6. I/O extended logouts are specified.
These settings cause the Model 145 to run in quiet mode fo~ hardware-
corrected errors. If the Model 145 is to operate in full recording
mode, the appropriate mask bits must be altered by the control program.
MACHINE CHECKS ON SYSTEM/360 MODELS 30 AND 40
A machine check situation in Models 30 and 40 results from hardware
detection of a machine malfunction or of a parity error. Bad parity can
occur in main storage, in local storage, in a register, in an adder,
etc. Error correction is not attempted by Model 30 or 40 hardware when
a machine check occurs (except for some instruction retry capability in
the Model 30). If the machine check mask in the current PSW (bit 13) is
enabled, a machine check causes an interruption and a diagnostic scan-
out occurs, starting at location 128. The number of bytes logged is
model dependent.
If an OS MFT or MVT SER routine for the Model 40 or the DOS HeRR
routine for the Model 30 or 40 is present, it gains CPU control after a
machine check interruption, and the error is logged. A retry of the
failing operation is not provided by these routines and the affected
program is terminated abnormally. If a recovery routine is not present,
the system is placed in a wait state when a machine check interruption
occurs.
(An
OS control program for a Model 40 must contain a machine
check handling routine, SERO or SER1, as of Release 17.)
RECOVERY MANAGEMENT SUPPORT (RMS) FOR OS MFT AND MVT
RMS for the Model 145 consists of extensions to the facilities
offered by RMS routines currently provided for Models 65 and up. The
two ~jS routines, machine check handler (MCR) to handle machine check
interruptions and channel check handler (CCH) to handle certain channel
errors, are included automatically in MFT and MVT control programs
generated for the Model 145.
The two primary objectives of RMS are
(l>
to reduce the number of
system terminations that result from machine malfunctions and (2) to
minimize the impact of such incidents. These objectives. are
accomplished by programmed recovery to allow system operations to
continue whenever possible and by the recording of system status for
both transient (corrected) and permanent (uncorrected) hardware errors.
Machine Check Handler
After IPL of a control program containing Model 145 RMS routines, the
recovery mask bit is on to permit recording of microinstruction retry
corrections, quiet mode is established for single-bit processor storage
corrections, threshold mode is established for single-bit control
storage corrections, and external interruptions are specified as are CPU
and I/O extended logouts. MCH receives· control after the occurrence of
machine check inte.rruptions for both repressible and exigent conditions.
Repressible Machine Checks. When a System Recovery machine check
occurs to indicate a successful microinstruction retry, MCB formats a
recovery report record to
be
written in the system error recording data
set SYS1.LOGREC. This record contains pertinent information about the
error, including the data in the fixed logout area, an indication of the
196 A Guide to the IBM System/370 Model 145