IBM System/370 145 Manual page 205

Error logging and the execuic.ion of recovery procedures are
required af,ter this type of interruption.
• System Damage. This interruption occurs if PSW bit
13
is on.
The
so
bit in the stored ma(::hine check code (bit
0)
is used to
indicate that an irreparabl~~ CPU failure occurred that was not a
resu! t of the execution of 1:.he instruction indicated in the
machine check old PSW. An unsuccessful retry of an interruption
or a wait state, control re~Jister damage, etc., are examples of
system damage errors.
systE~m
damage also is indicated if the
error cannot
be
identified as one of the other types of machine
check interruption. programmed error recovery is not possible
after this type of failure.
Modes of system Operation for Machine Check Interruptions
Two modes of system operation for machine check interruptions are
possible: full recording mode and quiet, or nonrecording, mode. In
full recording mode the CPU is enabled for all machine check
interruption types and all types cause an interruption to be taken and
logouts to occur except for intermittent single-bit storage error
corrections. This is the normal mode of Model 145 operation. In quiet
mode, the CPU is enabled for all OJ~ certain machine check interruptions
for repressible conditions. Quiet mode can be used to permit system
operation without error recording for all or certain repressible
conditions when a large number of t:ransient (correctable) errors are
occurring. It also can be used to allow Model 145 operation under the
control of an operating system without Model 145 machine check handling
routines included.
A
check-stop status and a check--stop-control bit have been defined
for the Model 145 (formerly called hard stop status and the hard stop
bit). The check-stop-control bit is located in control register 14 with
the other two mask bits discussed. If
a check-stop condition occurs,
the Model 145 system ceases all operations immediately without the
occurrence of a logout to the fixed area. Check-stop is initiated by
hardware rather than by programmingr.
Generally speaking, a check';"stop situation is caused by the
occurrence of an exigent machine
ct,~ck
condition during the processing
of a previous exigent machine check condition. Implementation of a
check-stop status prevents system operations from continuing when the
nature of the machine malfunction prevents the system from presenting
meaningful status data.
The state of the Model 145 aftez' IPL or a system reset is:
1 •
Recovery reports are not spE~cified. The processor storage
single-bit ECC correction mode bit is set to quiet mode and the
control storage ECC mode
bit~
is set to threshold mode for single-
bit corrections. Thus, succ:essful microinstruction retries and
single-bit ECC corrections on both control and processor storage
do not cause machine check i.nterruptions.
2.
External interruptions are s:pecif ied. Interval Timer Damage or
T'iming Facilities Damage causes a machine check interruption.
3. PSW
bit
13
normally is set t.o one by the IPL PSW (it is set to
zero by the IPL system reset procedure) to specify system Damage
and Instruction Processing Damage interruptions. Therefore, an
irreparable system error, an. unretryable CPU failure, an
unsuccessfully retried CPU failure, or a double-bit processor or
control storage error associated with instruction processing
causes an exigent machine check interruption.
~ G~ide
to the IBM System/310 Model 145 195