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SE4400 Integration Guide
*OBP = Optically Blocked Pixels, which are not photosensitive.
Figure 5-1. Pixel Layout
To operate properly, the CCD chipset requires a clock near 24 MHz. To achieve this, an
internal PLL multiplies the incoming 12 MHz MCKI by two to generate the 24 MHz internal
camera clock, MCK. (If using a 6 MHz MCKI, refer to the LC99704B-WK3 Sanyo DSP
Specification, Version 1). During pixel array read-out, the camera converts a pixel to an 8-
bit digital value at a rate of one half of MCK; therefore the pixel clock, PCLK, is generated
at a frequency of 12 MHz.
5-2
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