Figure 5.3 Low-Speed Internal Peripheral Bus Access Timing With Twe Phase - Hitachi HD64465 User Manual

Low-Speed Internal Bus Access Timing with TWe phase is shown in the Figure 5-3. The
diagram shows the cycles are T1, TWs1, TWs2, TWe and T2 phases. Note that there are two wait
states and one external peripheral hardware wait state in command cycle. In this case, the basic
command cycle is not enough for peripheral operation, it is responsible for the peripheral module
to insert its own wait signal before T2 stage. And the *WAIT# signal controlled by the peripheral
module must satisfy the setup/hold time defined in internal peripheral Bus AC timing
specifications. In Figure 5-3, the TWe stands for the external peripheral hardware wait state. The
command cycle can be inserted many TWe states, which depends on the signal *WAIT# of the
peripheral module. At the end of T2 phase, the question that either T1 or T_idle phase is followed
depends on the host CPU bus idle state configuration. If host CPU configures at least one idle state,
the corresponding T_idle phase is followed. If host CPU configures no idle state, the T1 phase is
followed after T2.
T1
CKIO
A20-A1
A24,A25
IMADDR
*MS#
IMRDWR#
IMRD#
(READ)
D31-D0
MODATA
IMWE0/1/2/3#
(WRITE)
D31-D0
MIDATA
*WAIT#

Figure 5.3 Low-Speed Internal Peripheral Bus Access Timing With TWe Phase

Rev. 3.0, 03/01, page 46 of 390
TWs1 TWs2
t
AD
t
MSD
t
RWD
t
RDD
t
WED
t
WDD
TWe
t
RDS
t t t
WDYS WDYH WDYS
T2 T_idle(T1)
t
MSD
t
RDD
t
RDH
t
WED
t
WDYH