Register Descriptions; A/D Data Registers A To D (Addra To Addrd, Adcal); Table 19.3 Analog Input Channels And A/D Data Registers - Hitachi HD64465 User Manual

19.2

Register Descriptions

19.2.1

A/D Data Registers A to D (ADDRA to ADDRD, ADCAL)

The five A/D data registers (ADDRA to ADDRD, ADCAL) are 16-bit read-only registers that
store the results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register
in correspondence to the selected channel. The lower 8 bits of the result are stored in the lower
byte of the A/D data register. The upper 2 bits are stored in the upper byte. Bits 15 to 10 of an A/D
data register are reserved bits that are always read 0. Table 19-3 below indicates the pairings of the
analog input channels and A/D data registers.
The CPU can always read the A/D data registers.
The A/D data registers are initialized to H'0000 by a reset.
Bit 15
ADDRn 0
(upper byte)
Initial Value 0
R/W -
Bit 7
ADDRn AD7
(lower byte)
Initial Value 0
R/W R
(n = A to D)

Table 19.3 Analog Input Channels and A/D Data Registers

Analog Input Channel (Value)
AN0
AN1
AN2
AN3
1/2VDD (1/2 x 3.3 Volt)
Rev. 3.0, 03/01, page 336 of 390
14 13 12
0 0 0
0 0 0
- - -
6 5 4
AD6 AD5 AD4
0 0 0
R R R
A/D Data Register
ADDRAX
ADDRBX
ADDRCX
ADDRDX
ADCAL
11 10 9
0 0 AD9
0 0 0
- - R
3 2 1
AD3 AD2 AD1
0 0 0
R R R
8
AD8
0
R
0
AD0
0
R