Signal Timing Description; Low Speed Timing; Figure 5.2 Low-Speed Basic Internal Peripheral Bus Access Timing - Hitachi HD64465 User Manual

5.4

Signal Timing Description

5.4.1

Low Speed Timing

HD64465 provides a programmable bit (SLS) in System Configuration Register (SCONFR) to
increase the system performance, depending on different bus clock (CKIO) rates. When SLS bit is
programmed with 1, the internal bus timing is switched to the basic cycle composed of two wait
states. When it is compared with High Speed Timing, a wait state will be found to save in
command cycle. Thus, the performance in low bus clock rate is increased.
Low-Speed Basic Internal Peripheral Bus Access Timing is shown in the Figure 5-2. These
basic cycles are T1, TWs1, TWs2, and T2 phases. Note that two wait states (TWs1, TWs2) are in
command cycle. In this case, no external peripheral hardware wait is asserted. The *WAIT# signal
is kept high before T2 stage. This means that peripheral module need no external cycles to
accomplish the command. So, the command cycle enters the T2 phase after TWs2. At the end of
T2 phase, the question that either T1 or T_idle phase is followed depends on the host CPU bus idle
state configuration. If host CPU configures at least one idle state, the corresponding T_idle phase is
followed. If host CPU configures no idle state, the T1 phase is followed after T2.
CKIO
A20-A1
A24,A25
IMADDR
*MS#
IMRDWR#
IMRD#
(READ)
D31-D0
MODATA
IMWE0/1/2/3#
(WRITE)
D31-D0
MIDATA
*WAIT#

Figure 5.2 Low-Speed Basic Internal Peripheral Bus Access Timing

T1 TWs1
t
AD
t
MSD
t
RWD
t
WDD
TWs2 T2
t
RDD
t
RDS
t
WED
t t
WDYS WDYH
Rev. 3.0, 03/01, page 45 of 390
T_idle(T1)
t
MSD
t
RDD
t
RDH
t
WED