Technical data
17.3 Technical specifications of the CPU 417–4H; (6ES7 417–4HT14–0AB0)
Data areas and their retentivity
Total retentive data area (incl. bit memory, timers,
counters)
Bit memory
•
•
Clock memory bits
Data blocks
•
Local data (selectable)
•
Blocks
OBs
•
Nesting depth
•
•
FBs
•
FCs
•
Address areas (inputs/outputs)
Total I/O address area
•
MPI/DP interface
DP interface
Process image
•
•
•
Access to consistent data in the process image
Digital channels
•
Analog channels
•
302
Retentivity selectable
Preset retentivity
Size
Preset
Size
Per priority class
Additional in an error OB
Size
Size
Distributed
Preset
Number of process image partitions
Consistent data
Central
Central
Total work and load memory (with backup battery)
16 KB
from MB 0 to MB 16383
from MB 0 to MB 15
8 (1 memory byte)
Maximum 8191 (DB 0 reserved)
Band of numbers 1 to 8191
Max. 64 KB
Max. 64 KB
32 KB
See instruction list
Max. 64 KB
24
2
Maximum 6144
Band of numbers 0 - 6143
Max. 64 KB
Maximum 6144
Band of numbers 0 - 6143
Max. 64 KB
16 KB/16 KB
incl. diagnostics addresses, addresses for I/O
interface modules, etc
2 KB/2 KB
8 KB/8 KB
16 KB/16 KB (programmable)
1024 bytes/1024 bytes
Max. 15
Max. 244 bytes
Yes
Max. 131072/
Max. 131072
Max. 131072/
Max. 131072
Max. 8192/
Max. 8192
Max. 8192/
Max. 8192
System Manual, 09/2007, A5E00267695-03
S7-400H