Technical data
17.2 Technical specifications of the CPU 414–4H; (6ES7 414–4HM14–0AB0)
Data areas and their retentivity
Total retentive data area (incl. bit memory, timers,
counters)
Bit memory
•
•
Clock memory bits
Data blocks
•
Local data (selectable)
•
Blocks
OBs
•
Nesting depth
•
•
FBs
•
FCs
•
Address areas (inputs/outputs)
Total I/O address area
•
MPI/DP interface
DP interface
Process image
•
•
•
Access to consistent data in the process image
Digital channels
•
Analog channels
•
294
Retentivity selectable
Preset retentivity
Size
Preset
Size
Per priority class
Additional in an error OB
Size
Size
Distributed
Preset
Number of process image partitions
Consistent data
Central
Central
Total work and load memory (with backup battery)
8 KB
from MB 0 to MB 8191
from MB 0 to MB 15
8 (1 memory byte)
Maximum 4095 (DB 0 reserved)
Band of numbers 1 - 4095
Max. 64 KB
Max. 16 KB
8 KB
See instruction list
Max. 64 KB
24
1
Maximum 2048
Band of numbers 0 - 2047
Max. 64 KB
Maximum 2048
Band of numbers 0 - 2047
Max. 64 KB
8 KB/8 KB
including diagnostic addresses, addresses for I/O
interface modules, etc.
2 KB/2 KB
6 KB/6 KB
8 KB / 8 KB (selectable)
256 bytes/256 bytes
Max. 15
Max. 244 bytes
Yes
Max. 65536/
Max. 65536
Max. 65536/
Max. 65536
Max. 4096/
Max. 4096
Max. 4096/
Max. 4096
System Manual, 09/2007, A5E00267695-03
S7-400H