Data Consistency - Siemens Simatic S7 Series System Manual

Communication
8.5 PROFIBUS
Configuration steps
The S7-200 SMART EM DP01 PROFIBUS DP module can be configured by the DP master
to accept output data from the DP master and return input data to the DP master. The output
and input data buffers reside in the variable memory (V memory) of the S7-200 SMART
CPU. When you configure the DP master, you define the byte location in V memory where
the output data buffer starts as part of the parameter assignment information for the
EM DP01. You also define the I/O configuration as the amount of output data to be written to
the S7-200 SMART CPU and amount of input data to be returned from the S7-200 SMART
CPU. The EM DP01 determines the size of the input and output buffers from the I/O
configuration. The DP master writes the parameter assignment and I/O configuration
information to the EM DP01. The EM DP01 then transfers the V memory address and input
and output data lengths to the S7-200 SMART CPU. These values are available in the
special memory (SM) of the S7-200 SMART CPU for use in the user program. Refer to the
SM status information in "User program considerations" (Page 384) for further details.
8.5.1.4

Data consistency

PROFIBUS supports three types of data consistency:
● Byte: Ensures that bytes are transferred as whole units
● Word: Ensures that word transfers cannot be interrupted by other processes in the CPU.
● Buffer: Ensures that the entire buffer of data is transferred as a single unit, uninterrupted
by any other process in the CPU.
The EM DP01 always utilizes buffer consistency in its data handling.
S7-200 SMART CPU and EM DP01 data buffer consistency
The EM DP01 and S7-200 SMART CPU offer buffer consistency for the entire transfer:
● The EM DP01 receives the outputs from the DP master in one message.
● The EM DP01 transfers all outputs to the S7-200 SMART CPU in one message that
cannot be interrupted.
● The S7-200 SMART CPU transfers all outputs to the V memory area at one time. The
transfer cannot be interrupted by a user interrupt.
The same consistency is true for the inputs to the DP master:
● The S7-200 SMART CPU transfers all inputs from the V memory at one time. The
transfer cannot be interrupted by a user interrupt.
● The S7-200 SMART CPU transfers all the inputs to the EM DP01 in one message. This
transfer cannot be interrupted.
● The EM DP01 sends the inputs to the DP master in one message.
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System Manual, 09/2015, A5E03822230-AC
S7-200 SMART