M66005-0001Ahp (Pd: Ic603); Pin Descriptions - Denon DCD-1500AE Service Manual

M66005-0001AHP (PD: IC603)

SEG02 49
SEG01 50
SEG00 51
Vcc2
52
53
SEG39
54
SEG38
DIG13 55
56
DIG12
M66005-0001AHP
57
DIG11
DIG10 58
59
DIG09
DIG08 60
DIG07 61
DIG06 62
DIG05 63
DIG04 64

PIN DESCRIPTIONS

Symbol
Pin name
Reset input
RESET
Chip select input
CS
Shift clock input
SCK
Serial data input
SDATA
Clock input
XIN ,
Clock output
XOUT
DIG00~
Digit output
DIG15
SEG00~
Segment output
SEG39
Universal port
P1 : bidirectional
P1, P0
P0 : output
Vcc1
Vcc2
Vss
Vp
( Connection of segment output pins )
Each square shows one-dot segment and the figure in
the square shows the output segment pin number
SEGnn (nn=00~39) to be connected.
SEG00~SEG34 are for character dot which are output
from character ROM or user RAM, and SEG35~SEG39
are the dot which is controlled by command.
BLOCK DIAGRAM
32
SEG19
31
SEG20
SEG21
30
SEG22
29
28 SEG23
CS
27 SEG24 14 Serial
26 SEG25
receive
SCK 15
SEG26
25
circuit
24 SDATA
Vp 16
23
SEG27
22 SEG28
21 SEG29
20 SEG30
19 SEG31
18
SEG32
XIN 21
Clock
SEG33
17
generator
XOUT 20
RESET
13
Vcc1
19
Vcc2
60
Vss 22
Vp
32
Comment
When "L", M66005A is initialized.
When "L", communication with the MCU is possible.
When "H", any instruction from the MCU is neglected.
Serial input data is taken and shifted by the positive edge of SCK.
When use as a CR oscillator, connect external resistor andcapacitor.
When use an external clock, input external clock to XIN, and XOUT
must be opened.
Connect to digit (grid) pins of VFD.
Connect to segment (anode) pins of VFD. Pins from SEG00 to SEG39
correspond to segment pins of VFD as shown in the table below.
SEG36~SEG39 pins are common to DIG12~DIG15 pins. So, when use
SEG36~SEG39, the number of digit to be used isdecreased.
Generally, use this port as the static output port.
This port also operateas s the timing IN/OUT port to control another
M66005A.
Positive power supply for internal logic.
Positive power supply for DIG and SEG outputs.
GND (0V)
Negative power supply to pull down.
33
.
Display code RAM
CGROM
Bank 1 : 8bit x 16
(35bit x 160)
Bank 2 : 8bit x 64
code
write
CGRAM
dot data
(35bit x 16)
write
Code/
data
command
. .
control
circuit
.
code
select
.
timing
Display
clock
controller
.
Front view of VFD
00 01 02 03
05 06 07 08
10 11 12 13
15 16 17 18
20 21 22 23
25 26 27 28
30 31 32 33
35
38
DCD-1500AE
.
. . .
. . .
59
Segment
33
.
output
. . . . . .
31
circuit
24
23
Segment/
64
Digit
63
select/
62
output
circuit
61
.
scan pulse
12
. .
Digit . .
.
output
. .
circuit
1
2
P0
18
17
04
09
14
19
24
29
34
39
. . .
SEG00
SEG26
. . .
SEG27
SEG34
SEG35
DIG12
DIG13
SEG38
SEG39
DIG00
. .
.
DIG11
P1