No.
Terminal Name
I/O
A/D
31 SYSCK
O
32 DV
18
P
DD
33 XI
I
34 XO
O
35 DV
P
SS
36 VDT7
O
37 VTD6
O
38 DV
P
SS
39 VDT5
O
40 VDT4
O
41 VDT3
O
42 VDT2
O
43 VDT1
O
44 VDT0
O
45 HDRQ
I
46 XHAC
O
47 VEFG
O
48 XSHD
O
49 DCK
O
50 DRVIRQ
O
51 DRVRST
I
52 DV
18
P
DD
53 DV
33
P
DD
54 DRVTX
O
55 DRVRX
I
56 DRVCLK
I
57 DRVRDY
O
58 C2PO
O
59 DADT
O
60 DOTX
O
61 LRCK
O
62 BCK
O
63 EXVCO
I
64 EXPLDT
I
65 CSL
O
66 SI
I
67 SO
O
68 SCLKH
O
69 RFOKGH
I
70 HFD
I
71 MIRRORH
I
72 DTC
I
73 AV
P
SS
74 ATC
I
75 HF
I
76 TLC0
O
77 TLC1
O
78 IREF
I
79 AV
33
P
DD
80 JMREF
I
81 JMOUT
O
82 CHG
I
83 VFBC
I
84 AV
18
P
DD
85 VCOI
I
86 LPF1
O
87 LPF2
O
88 RC
I
89 AV
P
SS
90 AV
P
SS
91 AD0
I
Classification
D
Clock
Clock Monitor output.
V
& GND
Digital 1.8V Power. (Internal logic system power)
DD
D
Clock
Crystal oscillation input.
D
Clock
Crystal oscillation output.
V
& GND
Digital Ground.
DD
D
VSTEM A/V
MPEG data output 7.
D
VSTEM A/V
MPEG data output 6.
V
& GND
Digital Ground.
DD
D
VSTEM A/V
MPEG data output 5.
D
VSTEM A/V
MPEG data output 4.
D
VSTEM A/V
MPEG data output 3.
D
VSTEM A/V
MPEG data output 2.
D
VSTEM A/V
MPEG data output 1.
D
VSTEM A/V
MPEG data output 0.
D
VSTEM A/V
MPEG data Request input.
D
VSTEM A/V
Data Valid output.
D
VSTEM A/V
ECC Error-sector Flag output. (L: error sector)
D
VSTEM A/V
DVD Sector Head Flag output.
D
VSTEM A/V
Data Strobe output.
D
VSTEM Command
Interrupt Request output for Host. (L: interruption is demanded)
D
VSTEM Command
Drive H/W Reset input. (L: reset)
V
& GND
Digital 1.8V power for Internal logic system.
DD
V
& GND
Digital 3.3V Power for I/O.
DD
D
VSTEM Command
Transmitting serial data output to Host.
D
VSTEM Command
Reception serial data input from Host.
D
VSTEM Command
Clock input from Host.
D
VSTEM Command
Drive Ready signal output. (L: ready)
D
Audio I/F
CD-DSP C2 Pointer output.
D
Audio I/F
Audio serial data output.
D
Audio I/F
Digital audio output.
D
Audio I/F
L/R Clock output.
D
Audio I/F
Audio Bit Clock output.
D
TEST/Monitor
External Channel clock input.
D
TEST/Monitor
External RF data input. (Logic level)
D
ASP I/F
SIO for RF signal processing LSI control. Latch signal output.
D
ASP I/F
SIO for RF signal processing LSI control. Serial data input.
D
ASP I/F
SIO for RF signal processing LSI control. Serial data output.
D
ASP I/F
SIO for RF signal processing LSI control. Serial clock output.
D
ASP I/F
RF O.K. Signal input.
D
ASP I/F
RF lack Signal input.
D
ASP I/F
Mirror detected signal input.(H: Mirror detected)
D
ASP I/F
Track cross signal input. (Logic level input)
V
& GND
Analog Ground.
DD
A
Data PLL
Track Cross signal input. (Analog level input)
A
Data PLL
RF signal input.
A
Data PLL
Asymmetry Charge-pump output 0.
A
Data PLL
Asymmetry Charge-pump output 1
A
Data PLL
Reference current setting terminal for Asymmetry Circuit.
V
& GND
Analog 3.3V Power.
DD
A
Data PLL
Reference current setting terminal for Jitter Monitor
A
Data PLL
Jitter Monitor output.
A
Data PLL
Reference current setting terminal for data PLL.
A
Data PLL
VCO offset frequency setting terminal for data PLL.
V
& GND
Analog 1.8V Power.
DD
A
Data PLL
VCO Control voltage input terminal for data PLL.
A
Data PLL
VCO Loop-filter connection terminal 1 for data PLL.
A
Data PLL
VCO Loop-filter connection terminal 2 for data PLL
A
Data PLL
VCO gain setting terminal for data PLL.
V
& GND
Analog Ground.
DD
V
& GND
Analog Ground.
DD
A
ADC
AD0 Input.
Function
22
DCD-1500AE
PU
PD
SMT
*
*
*
*
*
*
*
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