M30625Fgpgp (Sm: Ic739) - Denon DCD-1500AE Service Manual

M30625FGPGP (SM: IC739)

Pin Assignment
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
M30625FGNGP Port Assignment
pin port
1 VREF
2 AVCC
3 P97/ADTRG~/SIN4
4 P96/ANEX1/SOUT4
5 P95/ANEX0/CLK4
6 P94/DA1/TB4IN
7 P93/DA0/TB3IN
8 P92/TB2IN/SOUT3
9 P91/TB1IN/SIN3
10 P90/TB0IN/CLK3
11 P14_1
12 P14_0
13 BYTE
14 CNVss
15 P87/XCIN
16 P86/XCOUT
17 RESET~
18 XOUT
19 VSS
20 XIN
21 VCC
22 P85/NMI~
23 P84/INT2~
24 P83/INT1~
25 P82/INT0~
26 P81/TA4IN/U~
27 P80/TA4OUT/U
28 P77/TA3IN
29 P76/TA3OUT
30 P75/TA2IN/W~
31 P74/TA2OUT/W
P10/D8
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
P02/D2
P01/D1
P00/D0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
function I/O Initial
P97 O L OPEN
SOUT4 O L FDAT
CLK4 O L FCLK
P94 O L DSRST1
P93 O H GAL_RST
P92 O L OPEN
P91 I H USER1
P90 O L OPEN
O L OPEN
O H DSCS1
BYTE I BYTE
CNVss I CNVSS
P87 O L OPEN
P86 O H OPEN
RESET~ I RESET
XOUT O X.TAL
VSS - VSS
XIN I X.TAL
VCC - 3.3V
P85 I P_UP1
INT2~ I IR_IN
INT1~ I MINT
INT0~ I DRVIRQ
P81 I H OPEN
TA4OUT O L PWM
P77 O H SELDSD
P76 O H SMUTE
P75 O H DSDRST
P74 I MSREADY
mode
DIR_RST2
DISPLAY DATA for FL DRIVER
DISPLAY CLOCK for FL DRIVER
RESET for DAC (DSD1791)
RESET for GAL16V8
OPEN
MODEL SELECT 1 (10k P.U)
DL_ON
OPEN
CHIP SELECT for DAC (DSD1791)
PULL UP(8bit)
PULL DOWN (5.6k ohm)
CD_SEL (INTERNAL CD PLAY ONLT "H")
DSD_NORM (NORMAL DSD MODE ONLY "H")
RESET INPUT
OSC OUT
GND
OSC IN
POWER INPUT
10K PULL UP(NON CONECT)
IR INPUTSIGNAL (SHARP FORMAT)
INT from CXD1885Q
CXD1885Q DATA REQUEST
DL_IDD (DL ID WRITE MODE DETECTION ("L":Write Mode)
TRAY CONTROL PWM SIGNAL
SELECT for DSD SIGNAL(PLD)
MUTING for CXD2753R
RESET for CXD2753R
SERIAL DATA READY from CXD2753R
30
DCD-1500AE
P12_5
P12_6
P12_7
P50/WRL /WR
P51/WRH /BHE
P52/RD
P53/BCLK
P13_0
P13_1
P13_2
P13_3
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY /CLKOUT
P13_4
P13_5
P13_6
P13_7
P60/CTS0 /RTS0
P61/CLK0
P62/RXD0
P63/TXD0
P64/CTS1 /RTS1 /CTS0 /CLKS1
P65/CLK1
VSS
action NOTE
P.DN only
NOT USE