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59
CLK20MO
LED Interface
60
SPEED100#
61
DUP#
62
LINK&ACT#
10/100 PHY/Fiber
24
SD
25
AGND
26
BGRES
27
AVDD
28
AVDD
29
RX+
30
RX-
31
AGND
32
AGND
33
TXO+
34
TXO-
35
AVDD
Miscellaneous
16,17,18,
TEST1~TEST4
19
48
TEST5
68,69,70,
GPIO0~3
71
O
20Mhz clock output
It is used as the clock signal for the external MII device's clock is 20Mhz.
O
Speed LED
It is low output to indicate that the internal PHY is operated in 100M
speed, or it is floating for the 10M mode of the internal PHY.
O
Full-duplex LED
In LED mode 1, It is low output to indicate that the internal PHY is
operated in full-duplex mode, or it is floating for the half-duplex mode of
the internal PHY.
In LED mode 0, It is low output to indicate that the internal PHY is
operated in 10M mode, or it is floating for the 100M mode of the internal
PHY.
O
Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY.
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only.
I
Fiber-optic signal detect
PECL signal which indicates whether or not the fiber-optic receives pair is
receiving valid levels.
Bandgap ground.
I/O
Bandgap pin.
Bandgap and guard ring power
RX power
I
TP RX input
I
TP RX input
RX ground
TX ground
O
TP TX output
O
TP TX output
TX power
I
Operation Mode
Test1,2,3,4=(1,1,0,0) : the processor interface is ISA compatible.
Test1,2,3,4=(1,1,0,1) : the processor interface is for general processor .
I
It must be ground.
I/O
General I/O ports
Registers GPCR and GPR can program these pins.
The GPIO0 is output mode with output data high at default to power down
internal PHY and other external MII device.
GPIO1~3 default are input ports.
18
DN-V750/V755
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