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DM9000EP Terminal Function
Pin No.
Pin Name
MII Interface
37
LINK_I
41,40,39,
RXD[3:0]
38
43
CRS
44
COL
45
RX_DV
46
RX_ER
47
RX_CLK
49
TX_CLK
53,52,51,
TXD[3:0]
50
54
TX_EN
56
MDIO
57
MDC
Processor interface
1
IOR#
2
IOW#
3
AEN
4
IOWAIT
14
RST
6,7,8,9,10,
SD0~15
11,12,13,
89,88,87,
86,85,84,
83,82
Type
I
External MII device link status.
I
External MII Receive Data
I
External MII Carrier Sense
I
External MII Collision Detect
I
External MII Receive Data Valid
I
External MII Receive Error
I
External MII Receive Clock
I
External MII Transmit Clock
I/O
External MII Transmit Data
TXD[2:0] also used as the strap pins of IO base address when the DM9000 is
operated in ISA mode.
The IO base = (strap pin value of TXD[2:0]) * 10H + 300H
O
External MII Transmit Enable
I/O
MII Serial Management Data
I/O
MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin.
When the MDC pin is pull-high, the INT pin low active; otherwise the INT pin is
high active.
I
Processor Read command.
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail.
I
Processor Write command.
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail.
I
Address enable used for ISA mode or
chip select for general processor mode.
In general processor mode, the polarity of this pin can be modified by EEPROM
setting. See the EEPROM content description for detail.
O
Processor command ready
When a command is issued before last command completed, the IOWAIT will be
pulled to low to indicate the current command is waited.
I
Hardware reset command, high active to reset the DM9000.
I/O
Processor data bus bit 0~15
16
Description
DN-V750/V755
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