Denon UD-M31 Service Manual page 14

Pin No. Symbol I/O
42 LRSY O
43 CK2 O
ROMXA application
output signals
44 ROMXA O
45 C2F O
46 MUTEL O
LV
47
DD
48 LCHP O
49 LCHN O
LV
50
SS One-bit D/A converter
signals
RV
51
SS
52 RCHN O
53 RCHP O
RV
54
DD
55 MUTER O
56 DOUT O Digital output
57 SBSY O Subcode block synchronization signal output
58 EFLG O C1, C2, single and double error correction monitor pin
59 PW O Subcode P, Q, R, S, T, U and W output
60 SFSY O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state.
61 SBCK I Subcode readout clock input. This is a Schmitt input. (This pin must be connected to 0 V if unused.)
62 FSX O Output for the 7.35 kHz synchronization signal divided from the crystal oscillator
63 WRQ O Subcode Q output standby output
64 RWC I Read/write control input. This is a Schmitt input.
65 SQOUT O Subcode Q output
66 COIN I Command input from the control microprocessor
Input for the command input acquisition clock or the SQOUT pin subcode readout clock input. This is a Schmitt
67 CQCK I
input.
68 RES I Reset input. This pin must be set low briefly after power is first applied.
69 TST11 O Test output. Leave open. (Normally outputs a low level.)
70 LASER O Laser on/off output. Controlled by serial data commands from the control microprocessor.
71 16M O 16.9344 MHz output
72 4.2M O 4.2336 MHz output
73 CONT O Supplementary control output. Controlled by serial data commands from the control microprocessor.
74 TEST5 I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
75 CS I Chip select input. A pull-down resistor is built in. This pin must be connected to 0 V if unused.
XV
76 Crystal oscillator ground. Must be connected to 0 V.
SS
77 XIN I
Connections for a 16.9344 MHz crystal oscillator
78 XOUT O
XV
79 Crystal oscillator power supply
DD
80 TEST1 I Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
Note: All power-supply pins (V
L/R clock output
Bit clock output(after reset)
Interpolation data output(after reset)
C2 flag output
Left channel mute output
Left channel power supply
Left channel P output
Left channel N output
Left channel ground. Must be connected to 0 V.
Right channel ground. Must be connected to 0 V.
Right channel N output
Right channel P output
Right channel power supply
Right channel mute output
, VV , LV , RV , and XV
DD DD DD DD
Function
Inverted polarity clock output(during CK2CON
mode)
ROM data output (during ROMXA mode)
) must be connected to the same potential.
DD
14
UD-M31 14