Sfp Module Connector - Xilinx SP605 Hardware User's Manual

10. SFP Module Connector

The board contains a small form-factor pluggable (SFP) connector and cage assembly that
accepts SFP modules. The SFP interface is connected to MGT Bank 123 on the FPGA. The
SFP module serial ID interface is connected to the "SFP" IIC bus (see
information). The control and status signals for the SFP module are connected to jumpers
and test points as described in
Table
Table 1-12: SFP Module Control and Status
Table 1-13: SFP Module Connections
Notes:
1. The 125MHz SFP clock is sourced by clock driver U47.
2. Not P2 SFP module pins.
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
1-13.
SFP Control/Status Signal
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RT_SEL
SFP_LOS
U1 FPGA Pin Schematic Net Name
D13
C13
B14
A14
T17
Y8 SFP_TX_DISABLE_FPGA
A12 SFPCLK_QO_N
B12 SFPCLK_QO_P
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Table 1-12. The SFP module connections are shown in
Board Connection
Test Point J15
High = Fault
Low = Normal Operation
Jumper J44
On = SFP Enabled
Off = SFP Disabled
Test Point J16
High = Module Not Present
Low = Module Present
Jumper J22
Jumper Pins 1-2 = Full Bandwidth
Jumper Pins 2-3 = Reduced Bandwidth
Test Point J14
High = Loss of Receiver Signal
Low = Normal Operation
Pin Number
SFP_RX_P
SFP_RX_N
SFP_TX_P
SFP_TX_N
SFP_LOS
(1)
(1)
Detailed Description
14. IIC Bus for more
P2 SFP Module Connector
Pin Name
13 RDP
12 RDN
18 TDP
19 TDN
8 LOS
3 TX_DISABLE
(2)
U47.6 -
(2)
U47.7 -
33