Sharp TQ-GX30E Service Manual page 141

RESET_B
Reset
PLLDIV[2:0]
XOUT
Oscillation
circuit
XIN/
SCANCK
SCANCK
Current consumption
is decreased in a
standby mode.
BUFOFF_B
DB[15:0]
RSP
RD_B
WR_B
CS_B
WAIT_B
LCDINT
HSWRD
HSEN
HSCK
HSD[7:0]
DCS_B
DA[1:0]
EXCS_B[3:0]
RAM for BS mag/sol
For BS magnification function/
3D data sort function
LINE_Buffer (160 pixels x 48 x 4)
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
STKCHK
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PLL
Some MHz
Halt
to 68 MHz
Ctrl
PLL
Clock
Generator
Oscillation
ON/OFF
VideoDisplay IF
VDRD
Read Buffer
ReadDATA
6 bit x 4
RAM for mag/dif/sol
WriteDATA
For error diffusion
LINE_Buffer (160 pixels x 36 x 1)
CPU system
Buffer RAM for 1 line
buffer
For magnification function/
3D data sort function
LINE_Buffer (160 pixels x 48 x 4)
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
Buffer RAM for 1 line
Format conversion
circuit
VideoSignalProcessor
Conversion from YUV
Magnify
to RGB
Magnification
(Available for high-
circuit
speed pipelines)
Diffusion
Error diffusion
Pallet gamma circuit
circuit
Solidify
PalletRAM
3D circuit
Pallet
RAM(R)
8bitx256
72bit BS_DATA[71:0]
RAM(G)
RAM(B)
Buffer
BS circuit
18bitx4
SEL
Magnify
Solidify
Magnification
3D circuit
circuit
Bit Stream circuit A
Buffer section
BS_CLK
BUF_ BUF_
DATA0 DATA1
MCLK
phase
conversion
Commonly used
for sub-LCD
Buffer
VRAM
control
creation
Conversion
PIO for
from YUV to RGB
MPEG4ASIC
UV determination
control
and latch control
signal creation
YUVIN0,2
UV determination
and latch circuit
H/V effective
signal creation Conversion from
8-bit to 16-bit
manuals search engine
CONFIDENTIAL
MasterClock (MCLK) ····· VRAM/HOST/HS/BS/
Some MHz to 33 MHz VDIF/VSPetc
LCDTimingClock (TCLK)
····· TG/Pallet/LCD IF
5MHz~10MHz
/CDE/BS
SUBLCDTimingClock
····· SUB
(STCK) XIN clock
LowSpeedClock (LCLK)
····· SIO
100 kHz~200 kHz
PWMClock (PCLK)
····· PWM
XIN clock
MPEGClock (MPCLK)
·····External MPEG4_ASIC
15.36MHz or XIN
CameraClock (CAMCK)
·····External CAMERA_DSP
Approx.16.128 MHz
Registor
Available for
Bus
magnification
Controller
function
RACK
RACK
Memory Interface
·18 bit x 4
·Vertical and horizontal
access
WACK
(No limitation for the
WREQ
start address)
·Available for mask bit
72
Buffer
18bitx4
ColorDepthExpand
MaskBit Memory
320x240
Pixcel
(2bit)
Display Memory
Available for 6bit
MPEG4
320x240
Pixcel
6bit
(18bitx4
=72bit)
6bit
17bit
External
clock
Available for sub-LCD
output
130,000 colors
Equivalent to LR38840
17 8bit
I/F
Timing
4SCAN FRC
Control
6 – 21
FULL
TEST
Scan
Address
Generator
Display size
320 x 240
Pixel
260,000
colors
RW
Command
function
(Trans-
mission)
Available for
260,000 colors
RED
Pallet
BLUE
Pallet
R[5:0]
Palette
B[5:0]
I/F
CPU_DataBus
DB[7:0]
GX30
SE_LD2/PORT5
SE_LD3/PORT6
PWM0/PORT3
PWMLCD/PORT4
PWM1/PORT8
SE_DO/PORT0
SE_CK/PORT1
SE_LD1/PORT2
SE_DI/PORT7
DCLK
HSYNC
VSYNC
LCD
I/F
RDATA[5:0]
GDATA[5:0]
BDATA[5:0]