Power Control Integrated Circuit (Pcic); Temperature Cut Back Circuit; 700 Mhz Receiver - Motorola HT1250-LS+ Service Manual

3-12
3.8.3 Harmonic Filter
The harmonic filter is a modified Zolotarev design optimized for efficiency of the PA. It consists of a
combination of lumped components (C102-7, L101-2) and microstrip elements. This type of filter has
the advantage that it can give a greater attenuation in the stop-band for a given ripple level. The
design was optimized to meet critical attenuation requirements for the second harmonic in the 1559-
1610 MHz GNSS band. The harmonic filter insertion loss is typically less than 1 dB.
3.8.4 Antenna Matching Network
Because the 700 MHz antenna is a 50-ohm design, no matching circuitry is required between the
harmonic filter output and the 50-ohm SMA-style antenna connector (J101).
3.8.5

Power Control Integrated Circuit (PCIC)

The transmitter uses the PCIC (U102) to regulate the power output of the radio. The current to the
final device Q101 is supplied through resistor R116, that provides a voltage drop proportional to the
final device current drain. This voltage is then fed back to the automatic level control (ALC) within the
PCIC to regulate the output power of the transmitter. The PCIC contains internal digital to analog
converters (DACs) that provide a programmable control loop reference voltage. The PCIC internal
resistors, integrators, and external capacitors (C142, C144 and C146) control the transmitter rise and
fall times to reduce the power splatter into adjacent channels.
3.8.6

Temperature Cut Back Circuit

Temperature sensor U103 and associated components are part of a temperature cutback circuit. This
circuit senses the printed circuit board temperature around the transmitter circuits and outputs a DC
voltage to the PCIC. If the DC voltage produced exceeds the set threshold of the PCIC, the transmitter
output power decreases to reduce the transmitter temperature.
3.9

700 MHz Receiver

The 700 MHz receiver design is separated into two blocks, the front end and the back end. The overall
block diagram of the receiver is shown in Figure 3-11. Detailed descriptions of these stages are
contained in the paragraphs that follow.
Theory of Operation