Texas Instruments ADS42JB46 User Manual page 11

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Section
Reset and Power Down
Input Clock
Digital Gain Controls
Digital Test Patterns
Output Modes
Over Range Detection Controls
SLAU467D – November 2012 – Revised February 2017
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Table 3. ADC Controls Window Descriptions
Control
Device Reset
Stand By
Ch A Power Down
Ch B Power Down
Input Clock Divider
High Input Freq
Enable Gain A
Ch A Gain
Ch A FS Voltage
Enable Gain B
Ch B Gain
Ch B FS Voltage
Ch A Test Pattern
Ch B Test Pattern
Custom Pattern 1
Custom Pattern 2
Data Format
CML Drive Strength
Flip Data Bit Order
Which Ovr on Ovr Pin?
Fast OVR Threshold
Ch A Fast OVR Voltage
Ch B Fast OVR Voltage
ADS42JB46, ADS42JB49, and ADS42JB69 Evaluation Module
Copyright © 2012–2017, Texas Instruments Incorporated
Description
Automatically clears the device, so only a single mouse click
is needed
ADC is placed into standby mode. Both ADCs are powered
down (input clock buffer and CML output buffers are alive)
Turn ON and OFF channel A
Turn ON and OFF channel B
Internal clock divider for input sample clock
Change as necessary for input frequencies over or under
250MHz
Enables digital gain for channel A
Set gain for channel A between -2.7dB to 6dB
Automatically sets the equivalent Full-Scale Input Voltage
when the CH A Gain is set
Enables digital gain for channel B
Set gain for channel B between -2.7dB to 6dB
Automatically sets the equivalent Full-Scale Input Voltage
when the CH B Gain is set
Select from 12 different test patterns to be applied as inputs
to JESD block for channel A
Select from 12 different test patterns to be applied as inputs
to JESD block for channel B
Add in a custom 16-bit test pattern 1 for both channels
Add in a custom 16-bit test pattern 2 for both channels
Set the digital output data format
Changes JESD output buffer current
Output data order is reversed: MSB – LSB
Select if normal or fast OVR signal is presented on OVRA,
OVRB pins
Set the input voltage level at which the overload is detected.
The threshold at which fast OVR is triggered is (full-scale ×
[the decimal value of the FAST OVR THRESHOLD bits] /
127)
Overrange indication channel A (Ch A FS Voltage × [Fast
OVR Threshold / 127])
Overrange indication channel B (Ch B FS Voltage × [Fast
OVR Threshold / 127])
Software Operation
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