Header Pinout Configuration; Table 13. J2G1/J2G2/J2G3 Usb Port; Table 14. J2C1/J1C1Serial Port; Table 15. J2B1 Gpio Header - Intel QM77 User Manual

Reference Board Summary
4.1.3

Header Pinout Configuration

Table 13. J2G1/J2G2/J2G3 USB Port

There are three 2x5 Pin dual USB 2.0 headers on board.
Pin
1
3
5
7
9

Table 14. J2C1/J1C1Serial Port

 COM1: J2C1
 COM2: J1C1
Pin
1
3
5
7
9
Note: Please make sure the PCH CLKRUN# logic is "disable" OR Serial IRQ mode is
"continuous" in BIOS SETUP to enable the serial port.

Table 15. J2B1 GPIO Header

Pin
1
3
5
7
9
Note: The pins for GPIO are bi-directional signals. The factory default value is that Pins 1, 3,
5 and 7 are for TTL input while Pins 2, 4, 6 and 8 are for CMOS output. The factory
default status is high level while the voltage range for IO signals is 0-5V.
Intel® Core™ i5-3610ME Processor (PGA) and Mobile Intel® QM77 Express Chipset Development Kit
November 2012
Document Number: 328076-001
Signal Name
5V
USB1_Data-
USB1_Data+
GND
NA
Signal Name
DCD#
TXD
GND
RTS#
RI#
Signal Name
GPIO1
GPIO2
GPIO3
GPIO4
GND
Pin Signal Name
2 5V
4 USB2_Data-
6 USB2_Data+
8 GND
10 GND
Pin Signal Name
RXD
2
DTR#
4
DSR#
6
CTS#
8
NC
10
Pin Signal Name
2 GPIO5
4 GPIO6
6 GPIO7
8 GPIO8
10 NC
User Guide
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