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ZP94/95 CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PSD2
IOO1
2
1
Deflection PWB
SDA2
59
SCL2
60
U201
Data
Tuner 1
Enable
Clock
Main
FEENABLE1 44
6
U202
Data
Tuner 2
Enable
Clock
Pinp
FEENABLE2 43
17
SDA1
2
SCL1
3
SDA1
I003
DAC1
SCL1
SCL3
58
SDA3
57
20
2
Clock
21
3
Data
46
4
FCENAble
I014
DSPSS
15
5
3.3V -> 5V
Level Shift
16
6
DSPSCK
18
7
DSPERR Mute
17
8
DSPI
19
9
DSPRST
PYC1
Sweep Control
3
SCL2
I701
2
SDA2
16
SDA2
17
SCL2
34
SDA2
33
SCL2
PST1
5
1
4
2
16
5
15
6
5
6
6
5
PFC1
18
10
Clock
17
11
Data
16
12
Enable
FCEN
DSPSS
15
DSPSCK
14
DSPERR Mute
13
DSPI
12
DSPRST
11
Signal PWB
U204
3DY/C
PSZ2
I201
Main Video
Chroma
PSU1
I403
2
34
SDA2
Sub
1
Video
33
SCL2
Chroma
SDA
34
I401
1
A/V Select
33
SCL1
Terminal PWB
5
SDA1
IOO2
EEPROM
6
SCL1
SCL1
I004
DAC2
SDA1
SCL3
3
5
SDA3
4
4
U205
FLEX
&
PinP
PSU2
PMU1
DSPSS
5
DSPSCK
2
DSPERR Mute
6
DSPI
3
DSPRST
1
2H Video PWB
IX01
SCL2
2
26
Rainforest
RGB
SDA2
1
27
Processor
SDA2
SDA
4
2
SCL2
5
SCL2
SDA2
17
SCL2
16
SDA2
17
SCL2
16
SDA2
4
IS11
SCL2
5
Rear
Audio Control
SDA2
14
SCL2
15
9
12
DSP
8
Unit
HC4051
11
Surround PWB
13
IS03
Front
Audio
Control
IS05
Front
Equalizer
IS10
Center
Equalizer
IS08
Center/LFE/
PinP
Audio Control
IS01
DAC3
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