Intel S2600WF Technical Product Specification page 49

Intel® Server Board S2600WF Product Family Technical Product Specification
• Each installed processor provides six channels of memory. Memory channels from each processor are
identified as Channels A – F.
Each memory channel supports two DIMM slots, identified as slots 1 and 2.
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o On the server board, each DIMM slot is labeled by CPU #, memory channel, and slot # such as
CPU1_DIMM_A2 and CPU2_DIMM_A2.
• DIMM population rules require that DIMMs within a channel be populated starting with the blue DIMM
slot or DIMM farthest from the processor in a "fill-farthest" approach.
When only one DIMM is used for a given memory channel, it must be populated in the blue DIMM slot
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(furthest from the CPU).
• Mixing of DDR4 DIMM types (RDIMM, LRDIMM, 3DS RDIMM, 3DS LRDIMM, NVDIMM) within a channel
socket or across sockets produces a Fatal Error Halt during memory initialization.
• Mixing DIMMs of different frequencies and latencies is not supported within or across processor
sockets. If a mixed configuration is encountered, the BIOS attempts to operate at the highest
common frequency and the lowest latency possible.
When populating a quad-rank DIMM with a single- or dual-rank DIMM in the same channel, the quad-
•
rank DIMM must be populated farthest from the processor. Incorrect DIMM placement results in an
MRC error code. A maximum of 8 logical ranks can be used on any one channel, as well as a maximum
of 10 physical ranks loaded on a channel.
To install three quad-rank LRDIMMs on the same channel, they must be operated with rank
•
multiplication as RM = 2. This makes each LRDIMM appear as a dual-rank DIMM with ranks twice as
large.
The memory slots associated with a given processor are unavailable if the corresponding processor
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socket is not populated.
• A processor may be installed without populating the associated memory slots, provided a second
processor is installed with associated memory. In this case, the memory is shared by the processors.
However, the platform suffers performance degradation and latency due to the remote memory.
Processor sockets are self-contained and autonomous. However, all memory subsystem support
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(such as memory RAS and error management) in the BIOS setup are applied commonly across
processor sockets.
For multiple DIMMs per channel:
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o For RDIMM, LRDIMM, 3DS RDIMM, 3DS LRDIMM; always populate DIMMs with higher electrical
loading in slot1, followed by slot 2.
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