Denon DN-C640 Service Manual page 40

Q022 : JS28F128P30T85
Symbol Type
A[MAX:1] Input
Input/
DQ[15:0]
Output
ADV# Input
CE# Input
CLK Input
OE# Input
RST# Input
WAIT Output
WE# Input
WP# Input
Power/
VPP
Input
VCC Power
Symbol Type
VCCQ Power
VSS Power
RFU —
DU —
NC —
ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1];
512-Mbit: A[25:1].
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls
float when the CE# or OE# are deasserted. Data is internally latched during writes.
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: All chip enables must be high when device is not in use.
CLOCK: Synchronizes the device with the system's bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device's output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT's active output is V
V when CE# and OE# are V
OH
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
should not be attempted.
Set V = V for in-system program and erase operations. To accommodate resistor or diode
PP PPL
drops from the system supply, the V
above V min to perform in-system flash modification. VPP may be 0 V during read operations.
PPL
V can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PPH
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when
≤ V
V . Operations at invalid V
CC LKO
Output Power Supply: Output-driver source voltage.
Ground: Connect to system ground. Do not float any VSS connection.
Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These
should be treated in the same way as a Do Not Use (DU) signal.
Do Not Use: Do not connect to any other signal, or power supply; must be left floating.
No Connect: No internal connection; can be driven or floated.
Name and Function
. WAIT is high-Z if CE# or OE# is V
IL
≤ V
. Block erase and program at invalid V
PP PPLK
level of V can be as low as V
IH PP
voltages should not be attempted.
CC
Name and Function
54
OL
.
IH
voltages
PP
min. V must remain
PPL PP
or