Figure 2: Mixed DIMM load order
Table 7: DIMM pair load order
CPU0 only
Both CPUs loaded 1st
50
Optional components
CPU0
1st
3A
2nd
9B
3rd
1C
4th
7D
5th
2E
6th
8F
3A
2nd
—
3rd
9B
4th
—
5th
1C
6th
—
7th
7D
8th
—
CPU1
4A
—
10B
—
6C
—
12D
—
5E
—
11F
—
4A
—
—
1A
10B
—
—
6B
6C
—
—
3C
12D
—
—
4D
—
—
—
—
—
—
—
7A
—
10B
—
9C
—
12D
Table Continued