Yamaha YSP-4300 Service Manual page 96

YSP-CU4300/YSP-CU3300/NS-WSW160
Pin
Function Name
No.
T4 AXR1[11]/GP5[11]
N3 AXR1[10]/GP5[10]
M1 AXR1[9]/GP4[9]
M2 AXR1[8]/EPWM1A/GP4[8]
M3 AXR1[7]/EPWM1B/GP4[7]
M4 AXR1[6]/EPWM2A/GP4[6]
N1 AXR1[5]/EPWM2B/GP4[5]
N2 AXR1[4]/EQEP1B/GP4[4]
P1 AXR1[3]/EQEP1A/GP4[3]
P2 AXR1[2]/GP4[2]
R2 AXR1[1]/GP4[1]
T3 AXR1[0]/GP4[0]
K2 AHCLKX1/EPWM0B/GP3[14]
K3 ACLKX1/EPWM0A/GP3[15]
K4 AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
L1 AHCLKR1/GP4[11]
L2 ACLKR1/ECAP2/APWM2/GP4[12]
L3 AFSR1/GP4[13]
D4 AMUTE1/EPWMTZ/GP4[14]
B8 AXR0[0]/AFSR2/GP3[0]
D8 AXR0[2]/ AXR2[3]/GP3[2]
A7 AXR0[3]/ AXR2[2]/GP3[3]
B7 AXR0[4]/ AXR2[1]/GP3[4]
A5 AXR0[11]/AXR2[0]/GP3[11]
B5 AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
C8 AXR0[1]/ ACLKX2/GP3[1]
C7 AXR0[5]/ AFSX2/GP3[5]
R12 EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
D7 AXR0[6]/ ACLKR2/GP3[6]
T7 EMA_CS[3]/AMUTE2/GP2[6]
G4 USB0_DM
F4 USB0_DP
H5 USB0_VDDA33
E3 USB0_VDDA18
C3 USB0_VDDA12 (5)
D2 USB0_ID
D3 USB0_VBUS
E4 USB0_DRVVBUS/GP4[15]
B5 AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
R9 EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
P9 EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
M15 EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/
BOOT[13]
N13 EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
N15 EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
P13 EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
P15 EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
R13 EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
R15 EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
T13 EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/
BOOT[12]
K1 GP7[14] (6)
F7 RSV1
B1 RSV2
H4 NC
F3 NC
C1 NC
C2 NC
96
TYPE PULL
(1) (2)
I/O IPU McASP1 serial data
I/O IPU
I/O IPD
I/O IPD
I/O IPD
I/O IPD
I/O IPD
I/O IPD
I/O IPD
I/O IPD
I/O IPD
I/O IPD
I/O IPD McASP1 transmit master clock
I/O IPD McASP1transmit bit clock
I/O IPD McASP1 transmit frame sync
I/O IPD McASP1 receive master clock
I/O IPD McASP1 receive bit clock
I/O IPD McASP1 receive frame sync
O IPD McASP1 mute output
O IPD McASP2 serial data
O IPD
O IPD
O IPD
O IPD
O IPD McASP2 transmit master clock
O IPD McASP2 transmit bit clock
O IPD McASP2 transmit frame sync
O IPU McASP2 receive master clock
I/O IPD McASP2 receive bit clock
O IPU McASP2 mute output
Universal Serial Bus Module (USB0)
A USB0 PHY data minus
A USB0 PHY data plus
PWR USB0 PHY 3.3-V supply
PWR USB0 PHY 1.8-V supply input
PWR USB0 PHY 1.2-V LDO output for bypass cap
A USB0 PHY identification (mini-A or mini-B plug)
A USB0 bus voltage
O IPD USB0 controller VBUS control output
Multiplexed with GPIO bank 4 pin 15
I IPD USB_REFCLKIN. Optional 48 MHz clock input
Multimedia Card/Secure Digital (MMC/SD)
O IPU MMCSD_CLK
I/O IPU MMCSD_CMD
I/O IPU MMC/SD data
I/O IPU
I/O IPU
I/O IPU
I/O IPU
I/O IPU
I/O IPU
I/O IPU
General-Purpose IO Only Terminal Functions
I/O IPD General-Purpose IO signal
Reserved and No-connect
– – Reserved
(Leave unconnected, do not connect to power or ground)
PWR – Reserved
For proper device operation, this pin must be tied directly to CVDD
– –
– –
– –
– –
Detail of Function
–
–
–
–