Yamaha YSP-4300 Service Manual page 106

YSP-CU4300/YSP-CU3300/NS-WSW160
Pin Function I/O
No. Name (*1)
1 GPIO5 Is/O General-Purpose I/O pins
2 GPIO4 Is/O These I/O pin are assigned to the digital audio pins (WCK/BCK/SDIx/SDOx)
3 GPIO3 Is/O
4 DVSS –
5 GPIO2 Is
6 GPIO1 Is
7 GPIO0 Is
8 PLLVDD –
9 IC_N Is
10 PLLVSS –
11 PLLVSS –
12 XIN
13 XOUT O
14 IOVDD –
15 SCL Is
16 SDA Is/Od I2C control bus data I/O pin (not 5V tolerant)
17 OPEN –
18 DVSS –
19 IRQ_N Od
20 DVDD18 –
21 GPIO11 Is/O General-Purpose I/O pins
22 TESTb Is
23 DVSS –
24 OPEN –
25 DVSS –
26 GPIO10 Is/O General-Purpose I/O pins
27 GPIO9 Is/O These I/O pin are assigned to the digital audio pins (WCK/BCK/SDIx/SDOx)
28 GPIO8 Is/O
29 IOVDD –
30 GPIO7 Is/O General-Purpose I/O pins
31 DVDD18 –
32 GPIO6 Is/O General-Purpose I/O pins
*1
I/O symbols
I: Input pin Is: Schmitt trigger input pin
Is/Od: I/O pin (schmitt trigger input pin, Open-drain output pin)
*2
PLLVDD and DVDD18 should be same voltage because they are internally connected each other.
PLLVSS and DVSS pins are also internally connected as well.
*3
XIN pin input frequency
24.576MHz clock should be fed to XIN pin if MDSP2 firmware stored in the on-chip ROM is used.
*4
The figure below shows an example of connecting a crystal resonator.
Xin Xout
22.5792MHz
24.576MHz
* Select appropriate resistor and capacitor values according to the resonator's specification.
*5
OPEN pins must not be connected each other.
106
GND
General-Purpose I/O pins
These I/O pin are assigned to the digital audio pins (WCK/BCK/SDIx/SDOx)
PLL power supply ranging from 1.65V to 1.95V (*4)
Hardware reset pin (5V tolerant)
PLL GND (*2)
I Clock input pin
Connect a 22.5792MHz or 24.576MHz crystal resonator as shown in the example below (*3, 4)
When a crystal resonator is not used, feed a clock of 22.5792MHz or 24.576MHz to XIN pin
(Change the input clock frequency only when IC_N is at "L" level)
Clock output pin
Connect the external circuit as shown in the example below (*3)
When an external clock is directly fed to XIN pin without a crystal resonator, leave this pin open
Use this pin only for clock generation
Control interface power supply ranging from 3.0V to 3.6V
I2C control bus clock input pin (not 5V tolerant)
Leave this pin open (*5)
GND
Interrupt request output pin to the host controller (Interrupt request generating from DSP block)
Core power supply ranging from 1.65V to 1.95V
These I/O pin are assigned to the digital audio pins (WCK/BCK/SDIx/SDOx)
Test pin
Connect this pin to the GND
GND
Leave this pin open (*5)
GND
Control interface power supply ranging from 3.0V to 3.6V
These I/O pin are assigned to the digital audio pins (WCK/BCK/SDIx/SDOx)
Core power supply ranging from 1.65V to 1.95V
These I/O pin are assigned to the digital audio pins (WCK/BCK/SDIx/SDOx)
O: Output pin
Detail of Function
Od: Open-drain output pin Ot: Tri-state output pin
–: Power supply pin, GND pin
with AIFMD[3:0] register (5V tolerant)
with AIFMD[3:0] register (5V tolerant)
with AIFMD[3:0] register (5V tolerant)
with AIFMD[3:0] register (5V tolerant)
with AIFMD[3:0] register (5V tolerant)
with AIFMD[3:0] register (5V tolerant)
I/O: I/O pin