Control Register Details - Epson S1C17001 Technical Manual

6 INITERRUPT CONTROLLER

6.7 Control Register Details

Address Register name
0x4300 ITC_IFLG Interrupt Flag Register
0x4302 ITC_EN Interrupt Enable Register
0x4304 ITC_CTL ITC Control Register
0x4306 ITC_ELV0 External Interrupt Level Setup Register 0
0x4308 ITC_ELV1 External Interrupt Level Setup Register 1
0x430a ITC_ELV2 External Interrupt Level Setup Register 2
0x430c ITC_ELV3 External Interrupt Level Setup Register 3
0x430e ITC_ILV0 Internal Interrupt Level Setup Register 0
0x4310 ITC_ILV1 Internal Interrupt Level Setup Register 1
0x4312 ITC_ILV2 Internal Interrupt Level Setup Register 2
0x4314 ITC_ILV3 Internal Interrupt Level Setup Register 3
The ITC registers are described in detail below. These are 16-bit registers.
Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
40
Table 6.7.1 ITC register list
Indicates and resets interrupt occurrence status.
Permits/blocks maskable interrupts.
Permits/blocks ITC operation.
Sets P0 and P1 port interrupt level and trigger mode.
Sets stopwatch timer, clock timer interrupt level and trigger mode.
Sets 8-bit OSC1 timer interrupt level and trigger mode.
Sets PWM & capture timer interrupt level and trigger mode.
Sets 8-bit timer and 16-bit timer Ch.0 interrupt level.
Sets 16-bit timer Ch.1 and 16-bit timer Ch.2 interrupt level.
Sets UART and remote controller interrupt level.
2
Sets SPI and I C interrupt levels.
EPSON
Function
S1C17001 TECHNICAL MANUAL