Stopwatch Timer Interrupts - Epson S1C17001 Technical Manual

16 STOPWATCH TIMER (SWT)

16.6 Stopwatch Timer Interrupts

The SWT module includes functions for generating the following three kinds of interrupts:
• 100 Hz interrupt
• 10 Hz interrupt
• 1 Hz interrupt
The SWT module outputs a single interrupt signal shared by the above three interrupt factors to the interrupt con-
troller (ITC). The interrupt flag within the SWT module should be read to identify the interrupt factor that occurred.
100 Hz, 10 Hz, 1 Hz interrupts
Generated at the 100 Hz (approximate 100 Hz), 10 Hz (approximate 10 Hz), and 1 Hz signal falling edges,
these interrupt requests set the following interrupt flags in the SWT module to 1.
∗ SIF1:
1 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D2/0x5023)
∗ SIF10:
10 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D1/0x5023)
∗ SIF100: 100 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D0/0x5023)
To use these interrupts, set the following interrupt enable bits to 1 for the corresponding interrupt flags. If the
interrupt enable bits are set to 0 (default), the interrupt flag will not be set to 1, and the interrupt requests for
this factor will not be sent to the ITC.
∗ SIE1:
1 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D2/0x5022)
∗ SIE10:
10 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D1/0x5022)
∗ SIE100: 100 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D0/0x5022)
The SWT module outputs an interrupt request to the ITC if the SIF* is set to 1. This interrupt request signal
sets the stopwatch timer interrupt flag inside the ITC to 1 and generates an interrupt if the ITC and S1C17 core
interrupt conditions are met.
Check the frequency of a stopwatch timer interrupt by reading SIF* as part of the stopwatch timer interrupt
processing routine.
The interrupt factor should be cleared with the interrupt processing routine by resetting the SWT module SIF* (to
1) rather than the ITC stopwatch timer interrupt flag.
Note: To prevent generating unnecessary interrupts, reset the corresponding SIF* before permitting
stopwatch timer interrupt from SIE*.
Stopwatch timer interrupt ITC register
The stopwatch timer outputs an interrupt signal to the ITC using the falling edge for the frequency for which
interrupts are permitted in the settings previously described. To generate stopwatch timer interrupts, the inter-
rupt level and interrupt permission should be set in the ITC register.
The stopwatch timer ITC control bits are shown below.
Interrupt flag inside ITC
∗ EIFT2: Stopwatch Timer Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D2/0x4300)
Interrupt enable bit inside ITC
∗ EIEN2: Stopwatch Timer Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D2/0x4302)
Interrupt level setting bit inside ITC
∗ EILV2[2:0]: SWT Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV1) Register 1
(D[2:0]/0x4308)
Interrupt trigger mode selection bit inside ITC (Fix at 1)
∗ EITG2: SWT Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV1) Register 1
(D4/0x4308)
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S1C17001 TECHNICAL MANUAL